Commit Graph

144 Commits

Author SHA1 Message Date
Konstantin Belousov
43d5c9f65a Complete r277100: add AHCI_Q_ABAR0 tp AHCI_Q_BIT_STRING.
Noted and reviewed by:	smh
MFC after:	6 days
2015-01-13 09:50:15 +00:00
Konstantin Belousov
378c532c1f Add quirk to override default BAR(5) rid for AHCI.
Use it for Cavium AHCI.

Submitted by:	Michaе┌ Stanek
Reviewed by:	imp (previous version)
MFC after:	1 week
2015-01-13 00:11:56 +00:00
Marius Strobl
21190895ab - Const'ify the ahci_ids table.
- Use DEVMETHOD_END.
- Use NULL instead of 0 for pointers.

MFC after:	3 days
2014-12-28 20:42:28 +00:00
Steven Hartland
e4a8f2e2ec style (9) nits
Use return (val); instead of return val;

Differential Revision:	D838
MFC after:	2 weeks
Sponsored by:	Multiplay
2014-12-21 16:38:29 +00:00
Steven Hartland
5f59ea478e Return the error from ahci_setup_interrupt in ahci_attach
Previously ahci_attach returned a hard coded ENXIO instead of the value
from ahci_setup_interrupt. This is effectively a NOOP change as currently
ahci_setup_interrupt only ever returns 0 or ENXIO, so just there to protect
against any future changes to that.

Differential Revision:	D838
MFC after:	2 weeks
Sponsored by:	Multiplay
2014-12-21 16:32:57 +00:00
Steven Hartland
a12f5777df Clamp ahci max irq's to AHCI_MAX_IRQS
This prevents the possiblity of any overruns on the statically allocated
struct irqs field.

Differential Revision:	D838
MFC after:	2 weeks
X-MFC-With:	r276012
Sponsored by:	Multiplay
2014-12-21 16:15:29 +00:00
Steven Hartland
55972826f2 Add a constant AHCI_MAX_IRQS removing magic number
Sponsored by:	Multiplay
2014-12-21 16:07:46 +00:00
Alexander Motin
e67f3bec39 Add bunch of PCI IDs of Intel Wildcat Point (9 Series) chipsets.
MFC after:	1 week
2014-11-26 04:23:21 +00:00
Steven Hartland
85c9dd9d89 Prevent overflow issues in timeout processing
Previously, any timeout value for which (timeout * hz) will overflow the
signed integer, will give weird results, since callout(9) routines will
convert negative values of ticks to '1'. For unsigned integer overflow we
will get sufficiently smaller timeout values than expected.

Switch from callout_reset, which requires conversion to int based ticks
to callout_reset_sbt to avoid this.

Also correct isci to correctly resolve ccb timeout.

This was based on the original work done by Eygene Ryabinkin
<rea@freebsd.org> back in 5 Aug 2011 which used a macro to help avoid
the overlow.

Differential Revision:	https://reviews.freebsd.org/D1157
Reviewed by:	mav, davide
MFC after:	1 month
Sponsored by:	Multiplay
2014-11-21 21:01:24 +00:00
Ian Lepore
faab4473eb A dma tag alignment should be 1 (not 0) when a device can dma at any address. 2014-11-06 18:15:16 +00:00
Alexander Motin
88971a900d Use r271207 optimization only for MSI-enabled HBAs.
It was found that VirtualBox' AHCI does not allow nterrupt to be cleared
before the interrupt status register is read, causing interrupt storm.

AHCI specification allows to skip this register use when multi-vector MSI
is enabled and so interrupting port is known.  For single-vector MSI that
is not stated explicitly, but if the port is only one, it is obviously
known too.
2014-10-06 10:58:54 +00:00
Steven Hartland
6e9a599b27 Use a local STAILQ for unlocked done CCB processing in ahci direct mode
Previously it was possible for issues e.g. use after free, to result
from processing the done queue while not holding the channel lock.

While this should never happen in practice, unexpected code flows
which result in two threads processing from the same queue may
be possible.

We now use a local STAILQ to prevent this ever being an issue.

Sponsored by:	Multiplay
2014-09-27 19:14:22 +00:00
Alexander Motin
6e88c2c572 Initialize variables before resource_int_value().
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
2014-09-12 08:37:21 +00:00
Alexander Motin
03d89c944a Add PCI ID for Promise TX8660 8-port 3Gbps HBA.
This device reports RAID subclass, but appears to be AHCI compatible.

Submitted by:	Yuri Perejilin <yuri@rivera.ru>
MFC after:	1 week
2014-09-10 19:53:31 +00:00
Alexander Motin
fcd7f38fb0 Bunch of microoptimizations to reduce dereferences and cache collisions. 2014-09-08 12:11:49 +00:00
Alexander Motin
c45ff92177 Save one register read (AHCI_IS) for AHCI controllers with only one port.
For controllers with only one port (like PCIe or M.2 SSDs) interrupt can
come from only one source, and skipping read saves few percents of CPU time.

MFC after:	1 month
H/W donated by:	I/O Switch
2014-09-06 19:43:48 +00:00
Warner Losh
4acab041dd Restore order of interrupt setup. Minor problems can result by
setting up the interrupts too early:

Reviewed by: mav@
Sponsored by: Netflix
2014-09-06 18:20:50 +00:00
Alexander Motin
985da6db1c Fix typo in comments.
Submitted by:	Benedict Reuschling <bcr@FreeBSD.org>
MFC after:	6 days
2014-09-06 15:37:55 +00:00
Alexander Motin
c6efb4c41d Invert AHCI_Q_NOBSYRES quirk meaning, waiting for readiness by default.
I gave up to update list of Marvell chips that require this quirk.
The final nail was growing number of PCIe/M.2 SSDs where Marvell chips
have PCI IDs of different vendors.

MFC after:	1 week
H/W donated by:	I/O Switch
2014-09-05 13:45:14 +00:00
Warner Losh
802df3ace6 Separate out PCI attachment from the main AHCI driver. Move checks of
PCI IDs into quirks, which mostly fit (though you'd get no argument
from me that AHCI_Q_SATA1_UNIT0 is oddly specific). Set these quirks
in the PCI attachment. Make some shared functions public so that PCI
and possibly other bus attachments can use them.

The split isn't perfect yet, but it is functional. The split will be
perfected as other bus attachments for AHCI are written.

Sponsored by: Netflix
Reviewed by: kan, mav
Differential Revision: https://reviews.freebsd.org/D699
2014-09-04 22:22:53 +00:00
Warner Losh
0375d6f5f9 We were returning 20 bytes as the FIS size to send, but only
initializing 16. Initialize all 20 so we don't send garbage in the
Auxiliary register. The SATA standard mandates a 5 dword length for
the Host to Device FIS.

Sponsored by: Netflix
2014-08-30 02:13:09 +00:00
John Baldwin
a2677ff239 Don't bother clearing maps for static DMA allocations to NULL. Instead,
leave them as purely opaque values that are only set by bus_dmamem_alloc().
2014-06-17 18:10:06 +00:00
Alexander Motin
48ecfdc414 Correct AMD chipsets identification.
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	2 weeks
2014-04-17 14:16:02 +00:00
Alexander Motin
3fcad654e2 Add ID for one more ASMedia AHCI-compatible controller.
Reported by:	ignace.peeters@gmail.com
MFC after:	2 weeks
2014-01-17 17:16:49 +00:00
Zbigniew Bodek
b1c5afbb2f Revert r260165: Proper configuration of unmapped_buf_allowed should be used
To avoid failures in bus_dmamap_sync() on ARM unmapped_buf_allowed should
be set to 0. Hence, ARM-specific changes in AHCI should not be applied.
2014-01-02 11:24:04 +00:00
Zbigniew Bodek
49390e758d Use only mapped BIOs on ARM
Using unmapped BIOs causes failure inside bus_dmamap_sync, since
this function requires valid MVA address, which is not present
if mapping is not set up.

Submitted by:	Wojciech Macek <wma@semihalf.com>
Obtained from:	Semihalf
2014-01-01 20:26:08 +00:00
Zbigniew Bodek
df2ec2e4fb Do not attach to PCI bridges in AHCI driver
Some vendors use the same VID:PID combination in AHCI and PCI bridge cards

Submitted by:	Wojciech Macek <wma@semihalf.com>
Obtained from:	Semihalf
2014-01-01 20:18:03 +00:00
Alexander Motin
8adff99c8d Destroy mtx lock when failed to allocate memory during attach.
Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
MFC after:	2 weeks
2013-12-11 17:40:35 +00:00
Eitan Adler
7a22215c53 Fix undefined behavior: (1 << 31) is not defined as 1 is an int and this
shifts into the sign bit.  Instead use (1U << 31) which gets the
expected result.

This fix is not ideal as it assumes a 32 bit int, but does fix the issue
for most cases.

A similar change was made in OpenBSD.

Discussed with:	-arch, rdivacky
Reviewed by:	cperciva
2013-11-30 22:17:27 +00:00
Alexander Motin
9a6b4cb929 Add few more minor parts of DevSleep support from AHCI 1.3.1 proposal. 2013-11-15 15:14:07 +00:00
Alexander Motin
eda36fb4f5 Add some more IDs for Intel ATA, AHCI and USB controllers. 2013-11-15 10:28:59 +00:00
Alexander Motin
227d67aa54 Merge CAM locking changes from the projects/camlock branch to radically
reduce lock congestion and improve SMP scalability of the SCSI/ATA stack,
preparing the ground for the coming next GEOM direct dispatch support.

Replace big per-SIM locks with bunch of smaller ones:
 - per-LUN locks to protect device and peripheral drivers state;
 - per-target locks to protect list of LUNs on target;
 - per-bus locks to protect reference counting;
 - per-send queue locks to protect queue of CCBs to be sent;
 - per-done queue locks to protect queue of completed CCBs;
 - remaining per-SIM locks now protect only HBA driver internals.

While holding LUN lock it is allowed (while not recommended for performance
reasons) to take SIM lock.  The opposite acquisition order is forbidden.
All the other locks are leaf locks, that can be taken anywhere, but should
not be cascaded.  Many functions, such as: xpt_action(), xpt_done(),
xpt_async(), xpt_create_path(), etc. are no longer require (but allow) SIM
lock to be held.

To keep compatibility and solve cases where SIM lock can't be dropped, all
xpt_async() calls in addition to xpt_done() calls are queued to completion
threads for async processing in clean environment without SIM lock held.

Instead of single CAM SWI thread, used for commands completion processing
before, use multiple (depending on number of CPUs) threads.  Load balanced
between them using "hash" of the device B:T:L address.

HBA drivers that can drop SIM lock during completion processing and have
sufficient number of completion threads to efficiently scale to multiple
CPUs can use new function xpt_done_direct() to avoid extra context switch.
Make ahci(4) driver to use this mechanism depending on hardware setup.

Sponsored by:	iXsystems, Inc.
MFC after:	2 months
2013-10-21 12:00:26 +00:00
Gavin Atkinson
0d9bc65de7 Support the PCI-Express SSD in the new MacBook Air (model A1465)
Submitted by:	Johannes Lundberg <johannes brilliantservice.co.jp>
MFC after:	3 days
2013-08-28 14:29:33 +00:00
Alexander Motin
48f2741c29 Decode some bits defined in AHCI 1.3.1 Device Sleep Technical Proposal.
For now this is only conmetics to report HBA capabilities (Haswell?).

Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
2013-07-25 10:29:40 +00:00
Jack F Vogel
428e286da3 Add new Coleto Creek device support: SATA, SMBus, and Watchdog devices.
MFC after: 1 week
2013-07-19 21:37:40 +00:00
Alexander Motin
122ecf1eca Add ID for Marvell 88SE9215 AHCI SATA controller.
MFC after:	3 days
2013-07-09 08:49:17 +00:00
Alexander Motin
c4aea6be90 Add one more ID of Marvell SATA controller.
Submitted by:	marck
MFC after:	3 days
2013-07-09 08:32:17 +00:00
Steven Hartland
6fb5c84ea2 Added output of device QUIRKS for CAM and AHCI devices during boot.
Reviewed by:	mav
Approved by:	pjd (mentor)
MFC after:	2 weeks
2013-05-18 23:36:21 +00:00
Alexander Motin
943a5fa82e Add IDs for HighPoint RocketRAID 640L/642L/644L -- new series of 4-port
6Gbps PCIe 2.0 x2 SATA controllers, based on Marvell 88SE9235 chips.

MFC after:	1 week
2013-05-02 16:09:06 +00:00
Alexander Motin
234aa0297c Create controller-level DMA tag, handling range of supported addresses.
That simplifies logic for channels and gives the bus information about what
device actually allocated the tag.

Submitted by:	jhb@
2013-04-10 20:38:15 +00:00
Alexander Motin
c6eeee5e44 Check status of ahci_em_reset() on attach and abort if reset failed.
For now it is just a hypothetical case.

Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
2013-04-04 09:15:19 +00:00
Alexander Motin
6a740c4a4f Read Asynchronous Notification statuses only if Port Multiplier or ATAPI
device are connected. ATA disks are not using ANs, while the extra register
read operation is quite expensive.
2013-03-25 13:58:17 +00:00
Alexander Motin
3d44989055 Depending on combination of running commands (NCQ/non-NCQ) try to avoid
extra read from PxCI/PxSACT registers.  If only NCQ commands are running, we
don't really need PxCI.  If only non-NCQ commands are running we don't need
PxSACT.  Mixed set may happen only on controllers with FIS-based switching
when port multiplier is attached, and then we have to read both registers.

MFC after:	1 month
2013-03-25 08:50:51 +00:00
Alexander Motin
db12db318d No need to erase all 64 bytes of CFIS area if we never use more then 16. 2013-03-24 16:51:21 +00:00
Konstantin Belousov
129c6621f7 ahci(4) and siis(4) are ready to process the unmapped i/o requests
Sponsored by:	The FreeBSD Foundation
Tested by:	pho
Submitted by:	bf (siis patch)
2013-03-19 15:09:32 +00:00
Konstantin Belousov
dd0b4fb6d5 Reform the busdma API so that new types may be added without modifying
every architecture's busdma_machdep.c.  It is done by unifying the
bus_dmamap_load_buffer() routines so that they may be called from MI
code.  The MD busdma is then given a chance to do any final processing
in the complete() callback.

The cam changes unify the bus_dmamap_load* handling in cam drivers.

The arm and mips implementations are updated to track virtual
addresses for sync().  Previously this was done in a type specific
way.  Now it is done in a generic way by recording the list of
virtuals in the map.

Submitted by:	jeff (sponsored by EMC/Isilon)
Reviewed by:	kan (previous version), scottl,
	mjacob (isp(4), no objections for target mode changes)
Discussed with:	     ian (arm changes)
Tested by:	marius (sparc64), mips (jmallet), isci(4) on x86 (jharris),
	amd64 (Fabian Keil <freebsd-listen@fabiankeil.de>)
2013-02-12 16:57:20 +00:00
Alexander Motin
abd1548c8d Disable MSI interrupts for SB600 chipset. According to the report they are
not functional.

PR:		kern/174880, kern/174985, kern/175002
MFC after:	1 week
2013-01-24 09:33:43 +00:00
Jack F Vogel
e1d6f7b47b Add Intel Lynx Point PCH SATA Controller Device IDs 2013-01-02 22:26:46 +00:00
Alexander Motin
4587cbadc5 Add IDs for SATA controllers on AMD Hudson-2 series chipsets.
I am not exactly sure about the naming due to lack of specs on AMD site,
but it is better to have some identification then none at all.

MFC after:	1 month
2012-12-12 11:53:15 +00:00
Alexander Motin
aaff3a7331 Announce diagnostic page 7 (Element Descriptor) support. 2012-11-07 22:53:46 +00:00