bit 10 is the old bit for MTRR (presumably this changed, an older P5 I
have has got it, the newer cpus have the new MTRR bit set)
bit 11 is SEP (fast syscalls), bit 23 is MMX
Fill in the other reserved ones with a stub so that we can see them if
they turn up.
Obtained from: Intel AP-485 rev.06
license managers to obtain the host's ethernet address as
a key.
Note that this implementation takes the first hardware address for
the first ethernet interface found, and disregards the interface name
that may be passed in, as linux ethernet devices are all "ethX".
is incompatible with -pg. (We use a different version of mcount for
profiling frame-pointer-less assembler functions, but gcc doesn't know
about this.)
Added a missing dependency.
Cleaned up trailing backslashes.
Added comment about config's limitations/bugs handling dependencies and
backslashe/newlines.
Finished removing support for isdn drivers.
that lkm's can use them for fiddling the masks without being dependent on
which mode the kernel is compiled in (SMP or UP). This is particularly
for ppp_tty.c which has some domain crossing between the net and tty
subsystems. The values are not used in the spl code, they are for
reference only (ie: the compiled code uses immediate values rather than
an indirect 32 bit address and 32 bit data fetch).
top of the hardware interrupt handlers. Apparently this is slightly
faster with the bit scanning instruction that looks these up - this set of
changes reverts the original change.
Reviewed by: bde
rather than inlines. These are compiled with -fomit-frame-pointer and
work out pretty close to the original routines, but it might be a fraction
slower. The reason for doing this is to prevent the SWI_* and HWI_* values
from being compiled into drivers and lkms etc which is one of the things
that prevents the same lkm from being used on both SMP and UP kernels.
This gives us a lot more scope for experimenting with the splxxx
implementaton for SMP parallelism etc.
Reviewed by: bde
CPU code-named `M2'.
- Use the result of cpuid instruction instead of DIR to identify
6x86MX cpu. DIR0 and DIR1 are not documented in the data sheet, and
cpuid instruction is enabled at reset time.
- Add a function, init_6x86MX() to initialize 6x86MX cpu. It supports
CPU_SUSP_HLT and CPU_IORT options. It always sets NC1 (640K - 1M is
not cached.), and enables L1 cache in write-back mode.
- Fix typo in the comment in identblue().
Hopefully I've done the proper magic to merge changes between 1.17 and
1.17.2.1 into the main trunk. Description of those changes follows:
Brought in changes sent to me in late 1995 by Rich Murphey.
I cleaned up a few things and am currently running these under
2.2-970205-GAMMA.
The changes deal with software debouncing apparently necessary on
todays faster hardware, and also some problems with the use of the -Select
line for the TW-523 sync. This driver allows use of +PaperEnd as an
alternative.
Changes to pmap.c for lapic_t lapic && ioapic_t ioapic pointers,
currently equal to apic_base && io_apic_base, will stand alone with the
private page mapping.
apic.h has defines like:
#define lapic__id lapic->id
Once private pages and "known virtual addr" mapping of the APICs is
ready all 'lapic__XXX' will be changed to 'lapic.XXX', and the defines
will be removed.
Changes to smp.h for lapic_t lapic && ioapic_t ioapic pointers,
currently equal to apic_base && io_apic_base, will stand alone with the
private page mapping.
Adjust the data port address by adding the two low order bits of
the register number. The address port takes only a word address
(i.e. ignores the two low order bits written to it).
mode 1. Omission of this bit makes all config register accesses fail in
on recent chip sets ...
(The problem was reported and debug output provided by: Steve Passe)
