Commit Graph

11 Commits

Author SHA1 Message Date
ian
8d8c35656e Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't
have ACLE support built in.  The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available.  ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.

ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc.  Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use.  If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.

Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears.  Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.

Loves it:     imp
2016-05-25 19:44:26 +00:00
skra
41bb3cad44 Include pte-v6.h only where needed. 2016-02-17 12:57:05 +00:00
skra
87f75655f4 Make VM_MEMATTR_xxx definitions independent on pmap internals
for __ARM_ARCH >= 6.

It's TEX class number now, so it still has some meaning.
2016-02-04 14:15:24 +00:00
mmel
bce584a511 ARM: Rename ARM specific VM_MEMATTR_WT memory attribute to standard one. 2016-01-31 09:16:20 +00:00
mmel
eec4d6c027 ARM: remove old pmap-v6 code. The new pmap-v6 is mature enough, and
dual implementation is showstopper for major cleanup.

This patch only removes old code from tree. Cleanups will follow asap.
2016-01-29 10:31:54 +00:00
mmel
4a3bdaec00 ARM: create new memory attribute for writethrough cacheable memory.
- add new TEX class for WT cacheable memory
- export new TEX class to kernel as VM_MEMATTR_WT attribute
- add new aliases VM_MEMATTR_WRITE_COMBINING and
  VM_MEMATTR_WRITE_BACK, it's used in DRM code

Note:
 Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs,
 WT requests is treated as uncacheable.

Approved by:	kib (mentor)
2015-11-30 17:09:25 +00:00
ian
6fb7bdd343 New pmap code for armv6. Disabled by default, option ARM_NEW_PMAP enables it.
This is pretty much a complete rewrite based on the existing i386 code.  The
patches have been circulating for a couple years and have been looked at by
plenty of people, but I'm not putting anybody on the hook as having reviewed
this in any formal sense except myself.

After this has gotten wider testing from the user community, ARM_NEW_PMAP
will become the default and various dregs of the old pmap code will be
removed.

Submitted by:	Svatopluk Kraus <onwahe@gmail.com>,
	  	Michal Meloun <meloun@miracle.cz>
2015-03-26 21:13:53 +00:00
cognet
58faac84ca Properly implement pmap_[get|set]_memattr
Submitted by:	Ian Lepore <freebsd@damnhippie.dyndns.org>
2012-12-19 00:24:31 +00:00
alc
ea60573817 Add support to the virtual memory system for configuring machine-
dependent memory attributes:

Rename vm_cache_mode_t to vm_memattr_t.  The new name reflects the
fact that there are machine-dependent memory attributes that have
nothing to do with controlling the cache's behavior.

Introduce vm_object_set_memattr() for setting the default memory
attributes that will be given to an object's pages.

Introduce and use pmap_page_{get,set}_memattr() for getting and
setting a page's machine-dependent memory attributes.  Add full
support for these functions on amd64 and i386 and stubs for them on
the other architectures.  The function pmap_page_set_memattr() is also
responsible for any other machine-dependent aspects of changing a
page's memory attributes, such as flushing the cache or updating the
direct map.  The uses include kmem_alloc_contig(), vm_page_alloc(),
and the device pager:

  kmem_alloc_contig() can now be used to allocate kernel memory with
  non-default memory attributes on amd64 and i386.

  vm_page_alloc() and the device pager will set the memory attributes
  for the real or fictitious page according to the object's default
  memory attributes.

Update the various pmap functions on amd64 and i386 that map pages to
incorporate each page's memory attributes in the mapping.

Notes: (1) Inherent to this design are safety features that prevent
the specification of inconsistent memory attributes by different
mappings on amd64 and i386.  In addition, the device pager provides a
warning when a device driver creates a fictitious page with memory
attributes that are inconsistent with the real page that the
fictitious page is an alias for. (2) Storing the machine-dependent
memory attributes for amd64 and i386 as a dedicated "int" in "struct
md_page" represents a compromise between space efficiency and the ease
of MFCing these changes to RELENG_7.

In collaboration with: jhb

Approved by:	re (kib)
2009-07-12 23:31:20 +00:00
alc
1ce12d013e Correct the #endif comment.
Noticed by:	jmallett
Approved by:	re (kib)
2009-06-26 16:22:24 +00:00
alc
91cafd48b1 This change is the next step in implementing the cache control functionality
required by video card drivers.  Specifically, this change introduces
vm_cache_mode_t with an appropriate VM_CACHE_DEFAULT definition on all
architectures.  In addition, this changes adds a vm_cache_mode_t parameter
to kmem_alloc_contig() and vm_phys_alloc_contig().  These will be the
interfaces for allocating mapped kernel memory and physical memory,
respectively, with non-default cache modes.

In collaboration with:	jhb
2009-06-26 04:47:43 +00:00