Commit Graph

13 Commits

Author SHA1 Message Date
loos
1bfbe0af36 Remove the hardcoded limit for the number of gpio_pins that can be used.
Allocate it dynamically.

Approved by:	adrian (mentor)
2013-09-06 23:47:50 +00:00
loos
b6096f6e1e Fix an off-by-one bug in ar71xx_gpio and bcm2835_gpio which makes the last
pin unavailable.

Reported and tested by:	sbruno (ar71xx)
Approved by:	adrian (mentor)
Pointy hat to:	loos
2013-09-06 23:39:56 +00:00
adrian
e6cb6b38c2 Add a missing break. 2013-08-12 00:38:47 +00:00
adrian
e8a78f5357 Teach the GPIO code about the AR934x GPIO register and pin counts. 2013-07-21 03:55:18 +00:00
adrian
2c55b2f8ae Add the AR933x SoC GPIO pin count limitation. 2013-05-02 00:40:45 +00:00
dim
6a5be05861 Fix undefined behaviour in several gpio_pin_setflags() routines (under
sys/arm and sys/mips), squelching the clang 3.3 warnings about this.

Noticed by:	tinderbox and many irate spectators
Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
PR:		kern/177759
MFC after:	3 days
2013-04-13 21:21:13 +00:00
rpaulo
15835e923b The GPIO drivers were initialising their mutexes with type of
MTX_NETWORK_LOCK. This is wrong since these mutexes have nothing to do
with networking.
2012-08-17 04:44:57 +00:00
adrian
02336162cd Allow for a default GPIO pin "high", which is required for some boards
which tie the USB device enable to a GPIO line.

Submitted by:	Stefan Bethke <stb@lassitu.de>
2012-04-20 22:44:00 +00:00
adrian
d143e961c0 Remove these locks - they aren't strictly needed and cause measurable
performance issues.

* Access to the GPIO bus is already locked by requesting
  and releasing the bus - thus the lock isn't really needed
  for each GPIO pin change.
* Don't lock and unlock the GPIO bus for -each- i2c access -
  the i2c bus code is already doing this by calling the upper
  layer callback to request/release the bus. This thus locks
  the bus for the entirety of the transaction.

TODO:

* Further verify that everything is correctly requesting/
  releasing the GPIO bus.
* Look at how to lock the GPIO pin configuration stuff,
  potentially by locking/unlocking the bus at the gpiobus
  layer.
2011-12-20 00:33:56 +00:00
adrian
1af383c5f6 Re-jiggle the GPIO code a little to remove the hard-coded AR71xx GPIO
config and function mask setup.

* "gpiomask" now specifies which GPIO pins to enable, for devices to bind to.
* "function_set" allows bits in the function register to be set at GPIO setup.
* "function_clear" allows bits in the function register to be cleared at
  GPIO setup.

The function_set/function_clear bits allow for individual GPIO pins to either
drive a GPIO line or an alternate function - eg USB, JTAG, etc. This allows
for things like CS1/CS2 be enabled for those boards w/ >1 SPI device connected,
or disabling JTAG for the AR7240 (which is apparently needed ..)

I've verified this on the AR71xx.
2011-12-15 01:03:49 +00:00
adrian
94eb8448ed Fix GPIO_MAXPINS calculation for the AR71xx, AR724x, AR913x SoC.
Submitted by:	Luiz Otavio O Souza <loos.br@gmail.com>
2011-05-06 02:45:02 +00:00
gonzo
0dbb1afbee - Fix values of CS1_EN and CS2_EN flags
- Unbreak kernel build by fixing naming convention of
    GPIO_FUNC flags

Spotted by: Luiz Otavio O Souza, Andrew Thompson
2010-09-29 23:06:41 +00:00
gonzo
59f1565a72 Add AR71XX GPIO bus driver. 2010-09-28 03:31:34 +00:00