Commit Graph

14 Commits

Author SHA1 Message Date
bde
254458ab34 Fix printing of negative offsets (typically from frame pointers) again.
I fixed this in 1997, but the fix was over-engineered and fragile and
was broken in 2003 if not before.  i386 parameters were copied to 8
other arches verbatim, mostly after they stopped working on i386, and
mostly without the large comment saying how the values were chosen on
i386.  powerpc has a non-verbatim copy which just changes the uncritical
parameter and seems to add a sign extension bug to it.

Just treat negative offsets as offsets if they are no more negative than
-db_offset_max (default -64K), and remove all the broken parameters.

-64K is not very negative, but it is enough for frame and stack pointer
offsets since kernel stacks are small.

The over-engineering was mainly to go more negative than -64K for the
negative offset format, without affecting printing for more than a
single address.

Addresses in the top 64K of a (full 32-bit or 64-bit) address space
are now printed less well, but there aren't many interesting ones.
For arches that have many interesting ones very near the top (e.g.,
68k has interrupt vectors there), there would be no good limit for
the negative offset format and -64K is a good as anything.
2017-03-26 18:46:35 +00:00
ian
8d8c35656e Include machine/acle-compat.h in cdefs.h on arm if the compiler doesn't
have ACLE support built in.  The ACLE (ARM C Language Extensions) defines
a set of standardized symbols which indicate the architecture version and
features available.  ACLE support is built in to modern compilers (both
clang and gcc), but absent from gcc prior to 4.4.

ARM (the company) provides the acle-compat.h header file to define the
right symbols for older versions of gcc.  Basically, acle-compat.h does
for arm about the same thing cdefs.h does for freebsd: defines
standardized macros that work no matter which compiler you use.  If ARM
hadn't provided this file we would have ended up with a big #ifdef __arm__
section in cdefs.h with our own compatibility shims.

Remove #include <machine/acle-compat.h> from the zillion other places (an
ever-growing list) that it appears.  Since style(9) requires sys/types.h
or sys/param.h early in the include list, and both of those lead to
including cdefs.h, only a couple special cases still need to include
acle-compat.h directly.

Loves it:     imp
2016-05-25 19:44:26 +00:00
zbb
030d8a98be Introduce support for HW watchpoints and single stepping for ARMv6/v7
Allows for using hardware watchpoints for 1, 2, 4, 8 byte long addresses.
The default configuration of watchpoint is RW but code allows to select
RO or WO and X.
Since debugging registers are per-CPU (CP14) the watchpoint is set on
the CPU that was lucky (or not) to enter DDB.

HW breakpoints are used to perform single step in KDB.
When HW breakpoint is enabled all watchpoints are temporary disabled
to avoid recursive abort on both watchpoint and breakpoint.
In case of branch, the breakpoint is set to both - next instruction
and possible branch address. This requires at least 2 breakpoints
supported in the CPU however this is a must for ARMv6/v7 CPUs.

Reviewed by:   imp
Submitted by:  Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by:  Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4037
2016-01-25 18:02:28 +00:00
zbb
90fed1a09c Add support for branch instruction on armv7 with ptrace single step
Previous code supported only "continuous" code without any kind of
branch instructions. To change that, new function was implemented
which parses current instruction and returns an addres where
the jump might happen (alternative addr).
mdthread structure was extended to support two breakpoints
(one directly below current instruction and the second placed
at the alternative location).
One of them must trigger regardless the instruction has or has not been
executed due to condition field.
Upon cleanup, both software breakpoints are removed.

This implementation parses only the most common instructions
that are present in the code (like 99.99% of all), but there
is a chance there are some left, not covered by the parsing routine.
Parsing is done only for 32-bit instruction, no Thumb nor Thumb-2
support is provided.

Reviewed by:   kib
Submitted by:  Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by:  Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4021
2015-11-02 16:56:34 +00:00
ian
bd1ca6b379 Cleanup up ARM *frame structures...
- Eliminate unused irqframe
 - Eliminate unused saframe
 - Instead of splitting r4-sp storage between the stack and switchframe,
   just put all the registers in switchframe and eliminate the un_32 struct.

Submitted by:	Svatopluk Kraus <onwahe@gmail.com>,
		Michal Meloun <meloun@miracle.cz>
2014-12-24 18:54:31 +00:00
cognet
28def2c5ae Add "add pc, whatever" as a branch instruction, we use it in memcpy().
MFC after:	3 days
2008-08-03 15:35:32 +00:00
cognet
17ddb2b745 Add blx as a branch instruction.
MFC after:	3 days
2008-08-03 01:51:30 +00:00
cognet
91e09275cc Add yet another branch instruction.
Obtained from:	NetBSD
MFC after:	3 days
2008-08-02 12:48:30 +00:00
cognet
eb22761b8a Define BYTE_MSF if we're compiling a big endian kernel, so that DDB can
correctly disassemble instructions on big endian.
2006-07-27 11:41:37 +00:00
imp
77267e277f Start all license statements with /*- 2005-01-05 21:58:49 +00:00
cognet
22b168ab24 Implement breakpoints and single stepping on arm.
Obtained from:	NetBSD
2004-11-21 18:11:39 +00:00
cognet
75354c7e52 Implement enough to be able to enter and leave DDB. 2004-11-20 16:52:10 +00:00
cognet
1176e2e3a5 Update to kdb. 2004-07-12 21:25:01 +00:00
cognet
295dcdd687 Import FreeBSD/arm kernel bits.
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.
2004-05-14 11:46:45 +00:00