735 Commits

Author SHA1 Message Date
cognet
45301dddff Comment out the mapping of the OHCI controller registers va == pa. This
address is in the userland address space. The proper thing is either to choose
a virtual address in the kernel address space beyond the KVA, or to use
pmap_mapdev().
2006-07-12 00:48:50 +00:00
cognet
510c505cb5 Add a new flag to pmap_enter_locked() to say if it's OK to wait. If it is, and
we're unable to allocate the memory for a PTE, we'll wait until we can. If not,
we'll just return.
Use M_NOWAIT|M_USE_RESERVE to allocate PTEs, it is less aggressive than
M_NOWAIT alone.

Suggested by:   alc
2006-07-11 11:22:06 +00:00
imp
d1b6a98346 Add support for configuring pins to be one of {GPIO, PERIPHERAL A or
PERIPHERAL B}, as well as direction of GPIO pin.  Add defines for all
the pins.
2006-07-02 03:50:44 +00:00
imp
7a60ad8bb4 MFp4:
Make serial ports more robust and reliable.  Make non-console ports
work.  This might have broken skyeye stuff.

o Introduce ping-pong receive buffers.
o Use DMA to copy characters directly into memory.
o Support baud rates other than 115200
o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used,
  which caused dropped characters when received in bursts).
o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2
  stop bits were requested.
o Actually update line parameters.
o Fix comments
o Move init into attach
o Tweaks to TX interrupt registers to get them reliable and non-storming.
o harvest data in ipend since the latency between it and the callback
  was too long.  This likely is how it should be, I don't know why I deferred
  things to the callback before.
o disable all interrupts in console init.  We don't want interrupts until
  we turn on an ISR.
o cosmetic tweaks
o Automatically detect of the TIMEOUT interrupt is supported.  If so, use
  it so we get better CPU utilization.  Otherwise do a character at a time
  RX.  Good news here is that it seems we have enough CPU and low enough
  fast interrupt latency to do this reliably.
o Don't read USART_CR.  It is a write-only register.
o start to implement bus_ioctl.  Do BAUD now...
2006-07-02 03:45:33 +00:00
cognet
5688b2b9fa Backout previous commit, Warner committed at91_pio.c... 2006-06-23 23:07:11 +00:00
cognet
39fcd24d6a There's no need to allocate that much phdr/shdr from the stack. 2006-06-23 22:45:35 +00:00
cognet
905a22c391 Add the arm9_setup() prototype. 2006-06-23 22:37:15 +00:00
cognet
109db2df6d Comment out at91_pio.c, it's not in CVS. 2006-06-23 22:30:55 +00:00
cognet
73fb243aea arm9_setup() is now needed even if we're not using a gzipped kernel, so move
it outside the #ifdef KZIP

Pointy Hat to:	cognet
2006-06-22 22:33:21 +00:00
imp
14612d61da Nitsville: the routine is called initarm, not init_arm, correct it in
a comment.
2006-06-21 23:47:25 +00:00
cognet
bf915fdf74 Don't forget to define uart_sa1110_vaddr.
Submitted by:	kevlo
2006-06-21 10:56:59 +00:00
imp
7ac9e2a5c2 Compute physmem so we can print it correctly on boot.
Slightly optimize while I'm here.
2006-06-20 23:40:04 +00:00
imp
da7a558f2e Probe the memory size of the board better. Look at the bus width,
number of banks, rows and columns the SDRAMC is programmed to access
to determine the RAM size for the board, rather than hard-wiring it to
be 32MB.  My company's board with 64MB now probes correctly, as does
the KB9202 with only 32MB.  This means that to detect the right memory
size, our boot loader must correctly initialize these values.  This is
a fairly safe assumption because the boot loader has to initialize
SDRAM already, and it isn't really possible to change this register
after we've accessed SDRAM.
2006-06-20 20:13:40 +00:00
cognet
a32f908e29 Make sure the stack is properly aligned.
Enable the MMU when relocating as well, and use write-through cache.
2006-06-18 22:46:30 +00:00
imp
6126658315 comment out twi for now: no iicbus in KB920X: it breaks booting 2006-06-17 23:34:59 +00:00
imp
efe72c3bf7 Carefully note the RMII bit in the config register at attach time.
The boot loader is supposed to leave this bit set to the right value
for the board.  If this bit was set at attach time, use it to init the
config register correctly.

Note: this means the boot loader has to properly initialize it.
2006-06-17 23:24:35 +00:00
imp
c2756c87a0 improve reporting of clocks 2006-06-17 23:22:10 +00:00
netchild
11681ee0b5 Remove COMPAT_43 from GENERIC (and other kernel configs). For amd64 there's
an explicit comment that it's needed for the linuxolator. This is not the
case anymore. For all other architectures there was only a "KEEP THIS".
I'm (and other people too) running a COMPAT_43-less kernel since it's not
necessary anymore for the linuxolator. Roman is running such a kernel for a
for longer time. No problems so far. And I doubt other (newer than ia32
or alpha) architectures really depend on it.

This may result in a small performance increase for some workloads.

If the removal of COMPAT_43 results in a not working program, please
recompile it and all dependencies and try again before reporting a
problem.

The only place where COMPAT_43 is needed (as in: does not compile without
it) is in the (outdated/not usable since too old) svr4 code.

Note: this does not remove the COMPAT_43TTY option.

Nagging by:	rdivacky
2006-06-15 19:58:53 +00:00
ups
b3a7439a45 Remove mpte optimization from pmap_enter_quick().
There is a race with the current locking scheme and removing
it should have no measurable performance impact.
This fixes page faults leading to panics in pmap_enter_quick_locked()
on amd64/i386.

Reviewed by: alc,jhb,peter,ps
2006-06-15 01:01:06 +00:00
cognet
5dcde5a0f3 MFp4:
- Try hard to calculate a safe sp, so that the stack doesn't get smashed
while uncompressing or relocating the kernel.
- Bring in code needed to calculate the cacheline size etc, needed for
arm9_idcache_wbinv_all.
2006-06-12 22:58:50 +00:00
cognet
e928591f2a MFp4: Increase the L1 pagetable needed for the kernel from 8 to 22, to be
able to boot fat kernels.
2006-06-12 22:57:24 +00:00
alc
c282bd28da Remove pmap_pagedaemon_waken and update pmap_get_pv_entry() to match the
current interface with the machine-independent layer.  Without this change,
the page daemon would only have been awakened the first time that the
number of pv entries went above the high water mark, not each time.
2006-06-11 04:53:06 +00:00
alc
2047f3b7e7 Eliminate spl calls. 2006-06-11 04:14:36 +00:00
alc
2af67f3b97 Add a lock assertion. Remove dead (locking) code. Change some white
space.

Reviewed by: cognet@
2006-06-10 05:20:18 +00:00
alc
d902525710 Add pmap locking to pmap_extract().
Tested by: cognet@
2006-06-09 03:54:20 +00:00
cognet
b2f0652261 Oops it seems I forgot to remove ARM32_NEW_VM_LAYOUT from here. 2006-06-07 22:41:14 +00:00
alc
65c52763ef Add pmap locking to pmap_fault_fixup().
Add an assertion to pmap_vac_me_harder().

Tested by: cognet@
2006-06-07 20:54:31 +00:00
alc
0dc86d8ad0 Properly synchronize access to the pmap in pmap_extract_and_hold().
Eliminate an unneeded variable from pmap_extract_and_hold().

Tested by: cognet@
2006-06-07 17:14:48 +00:00
cognet
ef695e4fb6 Now that we use pmap_mapdev_boostrap(), we can get ride of the got_mmu
hack.

Submitted by:	kevlo
2006-06-07 11:28:17 +00:00
imp
21150f79c2 Remove sa1_cache_clean_addr. It isn't needed.
Submitted by: kevlo
2006-06-07 05:36:10 +00:00
cognet
13929c476a Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, and
completely nuke the !ARM32_NEW_VM_LAYOUT case.
2006-06-06 21:06:57 +00:00
cognet
5de6166e83 Remove a bogus, useless, "i++". 2006-06-06 20:47:59 +00:00
alc
0370c1b8e9 Add partial pmap locking.
Tested by: cognet@
2006-06-06 17:27:53 +00:00
alc
361dd71e9d Add partial pmap locking.
Eliminate the unused allpmaps list.

Tested by: cognet@
2006-06-06 04:32:20 +00:00
cognet
04175402f4 Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add it
as an option.

Submitted by:   Max N. Boyarov <m.boyarov at bsd dot by>
2006-06-06 01:14:12 +00:00
cognet
9a1fae8510 vm_page_alloc_contig() can sleep, so don't even think about using it
in the M_NOWAIT case.
2006-06-05 23:42:47 +00:00
alc
ff4adb11fe Introduce the function pmap_enter_object(). It maps a sequence of resident
pages from the same object.  Use it in vm_map_pmap_enter() to reduce the
locking overhead of premapping objects.

Reviewed by: tegge@
2006-06-05 20:35:27 +00:00
cognet
df0505f188 Don't #error if no CPU is defined but we're not compiling the kernel. 2006-06-02 09:39:06 +00:00
cognet
55e41f7b78 Don't enable the FIQ in enable_interrupts() if F32_bit is not specified.
This has been committed by mistake.

Reported by:	ssouhlal
2006-06-01 16:17:44 +00:00
alc
987bc104a2 Introduce pmap_enter_locked() and use it to reimplement pmap_enter_quick().
Tested by: cognet@
2006-06-01 01:31:07 +00:00
cognet
dab340c4af Avoid a LOR by unlocking the vm_page_queue_mtx before calling uma_zalloc,
and freeing the allocated memory if another thread already did the same.
2006-05-31 15:52:11 +00:00
cognet
25b7dd01d0 If our buffer is not aligned on the cache line size, write back/invalidate
the first and last cache line in PREREAD, and just invalidate the cache
lines in POSTREAD, instead of write-back/invalidating in POSTREAD, which
could lead to stale data overriding what has been transfered by DMA.
2006-05-31 15:50:33 +00:00
cognet
22b23b4b2d Ooops arm10 is armv5, not armv4.
Submitted by:	kevlo
2006-05-31 13:06:08 +00:00
cognet
d766c10a1c Include machine/cpuconf.h in pmap.h in order to get ARM_NMMUS defined,
to appease -Wundef.
2006-05-31 11:57:37 +00:00
cognet
9507be8d56 Protect the mapping used for pmap_copy_page/pmap_zero_page with a
mutex.
2006-05-30 23:50:45 +00:00
cognet
eb54945e83 To avoid problems, invalidate the data cache and disable the MMU once
we're done uncompressing the kernel.
2006-05-30 21:13:47 +00:00
cognet
032e8ffcc2 In pmap_is_prefaultable(), assert that the pte isn't NULL if
pmap_get_pde_pte() returns TRUE.

Suggested by:   ssouhlal
2006-05-30 16:55:38 +00:00
cognet
13f50bf79a The Assabet has 32MB of RAM, not 16.
Submitted by:	kevlo
2006-05-30 15:47:55 +00:00
benno
b96008e410 In pmap_mapdev we correctly round the address off to the nearest page
boundary, but we must also add the offset back on to the va we return.
2006-05-30 14:21:09 +00:00
cognet
6449092f51 Uncomment the call to cpu_idcache_wbinv_all() after the MMU has been
enabled. It has been commented out for a reason I forgot but I suspect
does not apply anymore.
Technically speaking it's not required to do it, has the data and the
instruction cache have been disabled in _start(). However, it may change
in the future, so I don't want to rely on this behavior.

Submitted by:	kevlo
2006-05-30 11:51:58 +00:00