the actual work. When USER_LDT is not defined for a kernel, sysarch returns
EOPNOTSUPP. Display a message in that case and return ENOSYS to userland.
Reviewed by: luoqi
1. Move definitions of struct i386_*_args to the header file sysarch.h,
since they are part of the sysarch API. struct i386_get_ldt_args and
i386_set_ldt_args were identical, therefore make them into one
struct i386_ldt_args. Libc should use these definitions as well.
2. Return a more sensible EOPNOTSUPP for unknown operations.
Reviewed by: marcel
`ED_P1_MAR + i' and `ED_P1_PAR + i', respectively.
- convert ED_PC_RESET and ED_PC_MISC into relative offset from
ED_PC_ASIC_OFFSET (those macros are not used in current source).
Submitted by: chi@bd.mbn.or.jp (Chiharu Shibata)
the new PnP code. Since the bulk of the driver changes are not being
committed at this time, it will not affect the driver. The code is being
committed early to allow others synchronise changes.
new system is integrated with the ISA bus code more cleanly and allows
the future addition of more enumerators such as PnPBIOS and ACPI.
This commit also enables the new pcm driver since it is somewhat tied to
the new PnP code.
Fix a bug where video capture locks up on channel changes.
Many thanks to Juha for solving this.
Submitted by: Juha Nurmela <Juha.Nurmela@quicknet.inet.fi>
Remove WD formatting code which has never worked in 386bsd or FreeBSD.
Remove DIOCSSTEP and DIOCSRETRIES ioctls as well, they belong in
history, along with the SMD disks.
OK'ed by: bde
* Make it possible to type a filename to boot1 so that it is possible to
recover from fatally broken versions of /boot/loader.
* Make a start at a CD boot program (not yet functional).
external NatSemi PHY chip was programmed to respond to MII address 24.
In the 3c905B ASICs, the transceiver is internal but it's still mapped
to MII address 24. But *some* 3Com 3c905B ASIC revisions map the
transceiver control registers to *all* MII addresses (0 through 31).
The miibus code probes for PHYs at all MII addresses and because of
this unusual behavior, it will attempt to map the same PHY registers
several times over, which doesn't work.
Naturally, the 3c905B NIC that I tested happened not to exhibit this
behavior.
The fix is to tweak xl_miibus_readreg() and xl_miibus_writereg()
to only respond when attempting to read from MII address 24. This
is safe to do since the 3Com documentation indicates that the PHY
and/or internal transceiver will always be mapped to address 24,
and there are no 3Com XL NICs with more than one PHY.
