6 Commits

Author SHA1 Message Date
das
3d86fb6387 Fix a problem relating to fesetenv() clobbering i387 register stack.
Details: As a side-effect of restoring a saved FP environment,
fesetenv() overwrites the tag word, which indicates which i387
registers are in use.  Normally this isn't a problem because
the calling convention requires the register stack to be empty
on function entry and exit.  However, fesetenv() is inlined, so we
need to tell gcc explicitly that the i387 registers get clobbered.

PR:	85101
2007-01-06 21:46:23 +00:00
das
5b7d321e53 Spell 'fedisableexcept' correctly. 2005-03-16 22:34:14 +00:00
das
6448887f3b Replace fegetmask() and fesetmask() with feenableexcept(),
fedisableexcept(), and fegetexcept().  These two sets of routines
provide the same functionality.  I implemented the former as an
undocumented internal interface to make the regression test easier to
write.  However, fe(enable|disable|get)except() is already part of
glibc, and I would like to avoid gratuitous differences.  The only
major flaw in the glibc API is that there's no good way to report
errors on processors that don't support all the unmasked exceptions.
2005-03-16 19:03:46 +00:00
das
4ec986eab3 Mark all inline asms that read the floating-point control or status
registers as volatile.  Instructions that *wrote* to FP state were
already marked volatile, but apparently gcc has license to move
non-volatile asms past volatile asms.  This broke amd64's feupdateenv
at -O2 due to a WAR conflict between fnstsw and fldenv there.
2005-01-14 07:09:23 +00:00
das
850b1bf882 Mark inline stmxcsr instructions as volatile, since this appears to be
the only way to convince gcc that they read the MXCSR.  The volatile
annotation may be needed elsewhere as well.
2005-01-11 22:10:43 +00:00
das
0252cb85b9 Add an fenv.h implementation for the amd64 port.
Reviewed by:	standards@
2004-06-06 10:03:25 +00:00