bridges in modern hardware (that hardware w/ lots of RAM). Raise the
address from 0x44000000 to 0x88000000 to match what we do with
NEWCARD. However, this really should be done in the pci layer.
o ToPIC is happy with two cards now, even when the two cards are
modems.
o Fix (all?) hangs on boot when power is applied to the card. I
suspect that this will make the Ricoh bridges happier and also
make a lot of VAIO owners happy (confirm to me in private email
please :-).
o All Cardbus bridges should now support 3.3V, X.XV and Y.YV cards,
to the extent that the underlying hardware supports such cards.
(X.X and Y.Y haven't been assigned values yet :-).
o Better 3.3V support for Ricoh ISA bridges.
How:
o Don't mess with the power register when scanning the cards. It
is unnecessary and causes BADVcc conditions on many chipsets. These
in turn can cause an interrupt storm.
o Make pcic_disable reset the slot's voltage.
o Move initializing voltage for the slot until after it has been
disabled.
o Fix a lot of issues with the pcic_cardbus_power routine. We
now properly enable the card and take it out of reset after
a power change.
o When detecting the card's voltage, if we're in a BadVcc state,
direct the bridge to rescan the card for what it supports.
(we might need to in the future set the power register to 0
before doing this).
o Don't preserve CLKSTOP. need to revisit this.
o Better support for Ricoh ISA bridges for 3.3V cards.
o Don't write to PCIC_POWER directly as offten, but instead go
through the pcic_power interface.
o All cardbus bridges now default to use cardbus power control.
o Add misc register definitions.
o remove some (now) bogus comments.
Extra Special Thanks To: Scott Lamber for his kind and generous loan
of a Toshiba laptop with a ToPIC 100 in it for my use.
o Bite the bullet and create controller types for the 6729 and also for
the 673x. Rename the 672x to 6722.
o Define minimal extended register info (just register 0xa for reading VS[12]).
# I think the last version may have broken 673x controllers, but this should
# fix them.
Tested on the 6722, but not the 6729.
Ideas from: Chiharu Shibata-san's article in bsd-nomads:15866
this accross suspend/resume events and this was causing the dreaded false
positive hit on my "static bug" test.
Note: the PCI bus code should do this for us.
Note2: We don't do the same for I/O based pci devices since it is
more code and doesn't appear to be necessary.
Submitted by: Toshiyuki Kawashima-san <tos@fa2.so-net.ne.jp>
Obtained from: bsd-nomads:16012
for initializing the parts. Since I don't have any of these parts in
any of my working laptops, I'm committing this to allow people to test
it. Will MFC when I receive reports of it working.
o Move initialization of the slot bst and bsh to inside the for loop.
o move sc there as well.
o Remove debug printf that prints the ID of the first slot twice.
o Use the sp for the relevant slot in getb, rather than for the 0th slot.
again? That NEVER works!" "This time for sure!"
Minor overhaul of how we do interrupts for the pci interrupt routing
case to cope with card ejection better (read: make it not hand on so
many cards):
o Reintroduce func_intr and func_arg and use the to store the
interrupt handler to call.
o Create a pcic_pci_func_intr to call the real interrupt handler
iff the card hasn't been ejected.
o Remove some checks in pcic_setup_intr now that it is used
exclusively for isa routed interrupts.
o Defer the eject event until later too, but make sure we can't
do any client driver ISR calling in the interrum.
o Add some simple code to make sure that we don't attach more
than one child. This should fix pccardd starting twice
problem (ala single user -> multi-user when you started pccardd
by hand in SU).
MFC: after jkh thinks I've put the crack pipe away.
When either bit 3 or 4 is set, we need to *SET* bit 5, not clear it in
the card control register. This makes TI PCI-1030, 1130 and 1131 not
work anymore without this fix.
MFC: soon
help with the hanging problem on reboot. Note: we need to do the
other things as well. Also, turn off the bits in the stat change
interrupt mask and the cardbus interrupt mask as well in an attempt to
shut off all interrupt sources.
# Note: The ToPIC 100 and the ToPIC 97 datasheets are in disagreement
# as to if this bit is supposed to be set or cleared to enable INTA routing
# so I made my best guess.
Also, comments about the various chipsets, including some grumpy ones
about how vague the O2micro datasheets are.
function and csc interrupt routing path (eg, ISA or PCI) so that we
can more easily switch between the two.
When we don't have a card ISR, put the function interrupt into ISA
mode. This effectively masks the interrupt since it happens once, and
not again until we have an ISR. This should help hangs, and might
help people that unwisely update the kernel w/o updating pccardd.
This is done at mapirq time.
Force CL-PD6729/30 to use ISA interrupt routing and maybe even detect
the number of pccard slots properly (this is still WIP). We aren't
going to support PCI interrupts for this release. A future release
should support them, however. Shibata-san's 3.3V fixes are not
included.
Add a hack which should, in i386, rewrite IRQ 0 cardbus bridges to be
IRQ 255, which should cause interrupts to be routed. This is mostly
untested since my one tester disappeared after reporting nothing
changed.
Implement, but do not use, a power method called cardbus. It looked
like a great way to get around the 3.3V problem, but it seems that you
can only use it to power cardbus cards (I get no CIS when I enable it,
so maybe we're programming things bogusly).
GC the intr and argp stuff from the slot database.
Improve the ToPIC support with the power hacks that Nakagawa-san
published in FreeBSD Press and that Hiroyuki Aizu-san ported to
-stable. The ToPIC hacks were for 3.3V support in ToPIC 100, but it
looks like the '97 also has identical registers, so use them too.
Add some #defines for the cardbus power stuff.
Finally implement making CSC on the Ricoh chips ISA or PCI. This will
allow polling mode to work on vaios, I think.
Add some minor debugging. This should likely be cleaned up or put
behing a bootverbose.
Some of this work, and earlier work, was influanced by Chiharu
Shibata-san's power handing patches posted to bsd-nomads:15866.
MFC: Soon, if possible.
config space that I'm aware of) work. I'm committing this from such
a machine.
Remove warning about I/O based bridges. Warn users that the PCI routing
of interrupts still doesn't work for these cards.
o For TI PCI-1130, you need to set bit 5 of register 91 if you want
ANY pci interrupts. Then set bits 3 and/or 4 as appropriate. This
will fix those people with 1030, 1130 and 1131 in their machines
trying to do PCI interrupts.
o Fix case where we were trying to automatically fail back to ISA
interrupt routing. We were dereferencing a NULL pointer. This
was true of ANY chipset.
o The bus_setup_intr method needs to be pcic_setup_intr so that "FAST"
interrupts fail on PCI case (modems act flakey if we don't force
them to fall back to normal interrupts). Also needed so that the
proper ISA IRQ can be set in the ExCA register. This fixes the
people whose ISA routing was failing[*].
o When we find a generic yenta/pccard bridge, go ahead and print its
vendor ID in boot verbose.
Machine with theses symptoms and a serial console by: jedgar
[*] Looks like my pc98 machine has some interrupt source on IRQ 15
that gave about 30 interrupts per second, which masked this problem on
my PC-9821Nr15.
interrupt for the CSC interrupt, then we revert to ISA. If we didn't
have an interrupt set up with hw.pcic.irq, then do polling.
Also, don't complain about ignoring function 1 for any devices except
pcic devices. This would normally only show up if someone set
hw.pcic.ignore_function_1=1.
MFC: as soon as I can test it on some troublesome laptops.
explain the subtle side effects that are going to happen and why we go
ahead and ack the interrupt source. This stuff is tricky to get
right.
Also, emperical tests have shown that doing a shutdown in attach to be
ineffectual, so remove it from there. Analysis of the code paths
shows that nearly identical writes to these registers happen in later
parts of the code. The hanging problem on thinkpads when we change
the interrupt routing type is something else.
shutdown and also before we get going with the device initialization.
This may fix the hangs some people are seeing on warmboot. It appears
that some machines will reset the cardbus bridge on boot, while others
don't. So we turn off the card, and ack the interrupts (which likely
is a nop in the shutdown case since we're still fielding interrupts).
This should turn off the interrupts.
Since I don't have hardware that hangs on reboot, I'm committing this
without testing that aspect of the patch (it causes no harm on my
Dell).
initialization structure. Warn the user for those chipsets that
aren't yet customized that they might not work. Second, try to power
off the slot on attach and ack the interrupts. I don't know, but this
might solve the hangs that people will see on Thinkpads if they set
hw.pcic.init_routing=1.
request and just calling it when we get a bridge interrupt. The
problem is that if other code wants to block hardware interrupts for a
little bit with splXXX, those masks aren't updated the way we're doing
it. This doesn't matter for -current, but does for -stable.
The whole reason that we were catching interrupts was to detect that
the card was still there. Ian's fixes however ensure that the card
will be there with an interrupt handler, or not there at all. Since
the pcic interrupt is at a high priority, this should be OK.
This should fix the network related crashes people started seeing in
stable after I merged the pcic as a pci device code.
Submitted indirectly by: Ian Dowse
MFC when: Ian has had a chance to do his torture hang testing.
the ISR. We keep track of the card state and don't call the IRS when
the card isn't inserted. This helps quite a bit with card ejection
problems that Ian was seeing.
Submitted by: Ian Dowse
MFC upon: re approvel.
register. It enables Zoom Video. It appears that on at least one
card that Monzoon is using sets these bits by default. Nothing works
when these bits are set, everything works when they are clear.
Add commentary on some of the ti bits. Make code a little clearer.
Also remove a call to pcic_pci_pd6729 which was prematurely added in
the last commit.
is the diagnostics register at offset 0x93. When bit 5 is set in this
register, bits 4-7 in ExCA register 0x5 being 0000 are required for
pci interrupt routing. When it is clear, then bit 4 of ExCA register
0x3 is used to enable it.
The only other issue is that when you route interrupts this way, you
must read ExCA register 0x4 in order to clear the interrupt, else you
get an interrupt storm.
Deal with this requirement by setting things up. It is believed that
this won't hurt other chipsets, but other chipsets may require their
own work arounds.
