This is a stub for PMSU driver. Note that it cannot be used to set the
secondary core boot address during attach because drivers are attached
later than SI_SUB_CPU sysinit where cores are started.
Setting the boot address should be done manually in platform_mp_start_ap().
SMP is working fine with this commit and was enabled in Armada38x kernel
configuration file.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4427
- Add file sys/arm/mv/armada38x/armada38x_mp.c
- Set mp_maxid and mp_ncpus based on FDT unless SCU register indicates
only one core
- Boot CPU1 in platform_mp_start_ap()
- IPI range defined
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4426
CPU1 is halted in bootROM code while it is waiting to be released.
Memory window to bootROM must be opened before booting the core.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4425
With this commit, watchdog is supported only in case of having
"mrvl,has-wdt" property or dedicated for watchdog compatibility field
("marvell,armada-380-wdt"). There is no need to modify dts files,
as "has-wdt" property already exists.
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4424
A38X watchdog support was implemented in sys/arm/mv/timer.c driver.
It required following modifications:
- add "marvell,armada-380-wdt" compatibility, which supports only watchdog
- correct and enhance definitions related to timer control register
- unmask reset capability in RSTOUTn_MASK register
- use dedicated watchdog timer on A38X instead of second timer
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4423
New driver registers RTC as system clock. New RTC resolution is 1 sec.
Settime and gettime functions were implemented.
Reviewed by: andrew, ian
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Jan Dabros <jsd@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4421
mv_pci driver omitted slot 0, which can be valid device on Armada38x.
New mechanism detects if device is root link, basing on vendor's
and device's IDs.
It is restricted to Armada38x; on other machines, behaviour remains
the same.
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4377
Add conditions corresponding to Armada38x-based SoCs,
enhancing their remap capabilities.
This is required for PCIe to work properly.
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4376
Add gic_decode_fdt function to fdt_pic_table, allowing to recognize GIC
interrupts on Armada38x. SOC_MV_ARMADA38X ifdef is required because A38X
is the only Marvell's platform in FreeBSD using GIC; lack of ifdef would
lead to linking errors on other platforms.
Reviewed by: andrew, ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4214
Strict compatibility requirement is a root of problems when simplebus'
node has two compatibility strings (i.e. on Armada38x). Removing this
requirement should not interfere with other platforms.
fdt_is_compatible_strict() and fdt_find_compatible() calls were changed
in fdt_common.c and mv_common.c.
Reviewed by: ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4602
This commit introduces initial support for Marvell Armada38x platform.
Changes:
- Add common DTS files for Armada38x SoCs and DTS file for A388-GP
- Add ARMADA38X kernel configuration
- Add option SOC_MV_ARMADA38X and set MV_PCI_PORTS
- Add list of files to compile
- Implement get_tclk(), get_sar_value(), cpu_reset() functions
- Add CPU ID and SoC numbers
- Correct ifdefs in arm/mv/timer.c
Reviewed by: ian, imp
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Michal Stanek <mst@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4210
Including arm/mv/gpio.c now depends on 'gpio' device. 'device gpio' was
added to all kernconf files of Marvell boards, except ARMADAXP (dummy
mv_gpio_res definition was removed) and ARMADA38X (not supported yet).
This commit allows to use generic files.mv on A38X.
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Stormshield
Submitted by: Bartosz Szczepanek <bsz@semihalf.com>
Differential revision: https://reviews.freebsd.org/D4372
match the physical load address. Remove the *PHYSADDR symbols which are no
longer necessary.
Also remove a bunch of comments, most of which which have been wrong for
quite some time now, and the rest of which are mooted by these changes. All
that's left in this file is assigning a single symbol to its cannonical
value, not much to comment on anymore.
variable during mp_start() which is too late. Move this to mp_setmaxid()
where other architectures set it and move x86 assertions to MI code.
Reviewed by: kib (x86 part)
value is defined as a config option the definition is emitted into
opt_global.h which is force-included into everything. In addition, the
symbol is emitted by the genassym mechanism, but that by its nature reduces
the value to a 0xnnnnnnnn number. When compiling a .S file you end up
with two different definitions of the macro (they evaluate to the same
number, but the text is different, upsetting the compiler).
Nothing has changed about this code for a while but the compile error is
new, so this must be fallout from the clang 3.7 update or something.
missed. In other words, if a new request for an IPI is sent while the
previous request is being handled but the IPI is not cleared yet, the
clearing of the previous IPI request also clears the new one and the
handling is missed.
There are only three MP interrupt controllers in ARM now. Two of them are
fixed by this change, the third one is correct, probably only just by
accident. The fix is minimalistic as new interrupt framework is awaited.
It was debugged on RPi2 where missing IPI handling together with SCHED_ULE
led to situation in which tdq_ipipending was not cleared and so IPI_PREEMPT
was stopped to be sent. Various odditys were found related to slow system
response time like various events timed out, and slow console response.
Submitted by: Svatopluk Kraus <onwahe@gmail.com>
Reviewed by: loos, kib
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D3722
the startup trampoline code. The old code allocated a kva page, mapped it
using using pmap_kenter_nocache(), then freed the kva without destroying
the mapping. This is the only use of pmap_kenter_nocache() in the system,
so redoing this one use of allows it to be garbage collected in the
near future.
SoC's registers base address may differ between boards
(0xf1000000 or 0xd0000000). Therefore, in order to use
the proper CPU Boot Address Redirect register during SMP
initialization in mptramp the real, physical address has
to be passed to mptramp based on the value from DT.
Reviewed by: gber
During Armada's platform_mp_start_ap(), mptramp code
is being copied to the specific physical location (0xffff0000).
Before r265694 the address to which the code should be copied
was equal to the address of mpentry routine that followed the
mptramp in locore.S. Now the mptramp end address should be
exported and used as a copy limit.
Reviewed by: gber
platform code, it is expected these will be merged in the future when the
ARM code is more complete.
Until more boards can be tested only use this with the Raspberry Pi and
rrename the functions on the other SoCs.
Reviewed by: ian@
On armv4 these are defined as synonyms right now, but it's a bit ambiguous
what NOCACHE means (is buffering/write-combining also enabled or not?); this
is a first step towards replacing PTE_NOCACHE with a less ambiguous name.
and the functionality it provided into arm/exception.S. Rename the main
irq handling routine from arm_handler_execute() to arm_irq_handler() to
make it more congruent with how other exception handlers are named, and
also update its signature to reflect what has long been reality: it is
passed just a trapframe pointer, no interrupt number argument.
