Commit Graph

21 Commits

Author SHA1 Message Date
br
68c30b183a o Remove operation in machine mode.
Machine privilege level was specially designed to use in vendor's
  firmware or bootloader. We have implemented operation in machine
  mode in FreeBSD as part of understanding RISC-V ISA, but it is time
  to remove it.
  We now use BBL (Berkeley Boot Loader) -- standard RISC-V firmware,
  which provides operation in machine mode for us.
  We now use standard SBI calls to machine mode, instead of handmade
  'syscalls'.
o Remove HTIF bus.
  HTIF bus is now legacy and no longer exists in RISC-V specification.
  HTIF code still exists in Spike simulator, but BBL do not provide
  raw interface to it.
  Memory disk is only choice for now to have multiuser booted in Spike,
  until Spike has implemented more devices (e.g. Virtio, etc).

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-08-10 12:41:36 +00:00
br
1167f0cf7c Update RISC-V port to Privileged Architecture Version 1.9.
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-08-02 14:50:14 +00:00
br
5bdc642eff Remove duplicate define. 2016-06-08 13:57:18 +00:00
br
5884cd6a83 Increase the size and alignment of the setjmp buffer.
This is required for future CPU extentions.

Reviewed by:	brooks
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-05-26 10:03:30 +00:00
br
501a9d9525 Add initial DTrace support for RISC-V.
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-05-24 16:41:37 +00:00
br
a4f12ac788 Rework the list of all pmaps: embed the list link into pmap. 2016-04-26 14:38:18 +00:00
br
be0f4b3117 Add the non-standard "IO interrupt" vector used by lowRISC.
For now they provide UART irq only.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-04-26 12:56:44 +00:00
br
778cc5a811 Move arm's devmap to some generic place, so it can be used
by other architectures.

Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D6091
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-04-26 11:53:37 +00:00
br
7b9e9617a5 o Implement shared pagetables and switch from 4 to 3 levels page
memory system.

RISC-V ISA has only single page table base register for both kernel
and user addresses translation. Before this commit we were using an
extra (4th) level of pagetables for switching between kernel and user
pagetables, but then realized FPGA hardware has 3-level page system
hardcoded. It is also become clear that the bitfile synthesized for
4-level system is untested/broken, so we can't use extra level for
switching.

We are now share level 1 of pagetables between kernel and user VA.
This requires to keep track of all the user pmaps created and once we
adding L1 page to kernel pmap we have to add it to all the user pmaps.

o Change the VM layout as we must have topmost bit to be 1 in the
  selected page system for kernel addresses and 0 for user addresses.
o Implement pmap_kenter_device().
o Create the l3 tables for the early devmap.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-04-25 14:47:51 +00:00
br
0022e5410b Add support for ddb(4).
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-03-10 15:51:43 +00:00
br
5f4b8a7cdb o Use uint64_t for page number as it doesn't fit uint32_t.
o Implement growkernel bits for L1 level of pagetables.

This allows us to boot with 128GB of physical memory.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-02-26 14:04:00 +00:00
br
c6609a6326 Add support for symmetric multiprocessing (SMP).
Tested on Spike simulator with 2 and 16 cores (tlb enabled),
so set MAXCPU to 16 at this time.

This uses FDT data to get information about CPUs
(code based on arm64 mp_machdep).

Invalidate entire TLB cache as it is the only way yet.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-02-24 16:50:34 +00:00
br
f20a04ba12 Remove duplicates. 2016-02-22 14:13:05 +00:00
br
2da7acfc05 Increase kernel and user VA space.
This allows us to boot with more than 128MB of physical memory.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-02-18 15:28:57 +00:00
br
ab7fae640a Add the implementation of atomic_swap_32(). 2016-02-17 14:32:03 +00:00
br
633cf96bb1 Use better form representing 32 x 128-bit floating-point registers.
Suggested by:	kib
2016-02-17 14:24:25 +00:00
br
7fd7c903a3 Use __uint64_t type for floating point registers
as compiler don't know about __uint128_t yet.

Discussed with:	theraven, kib
2016-02-12 14:29:14 +00:00
br
996520c667 Access pcpup using gp register. 2016-02-04 14:30:46 +00:00
br
a6a53aa0dc Reuse gp register for pcpu pointer.
gp (global pointer) is used by compiler in userland only,
so re-use it for pcpup in kernel, save it on stack on switching
out to userland and load back on return to kernel.

Discussed with:	jhb, andrew, kib
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D5178
2016-02-04 12:49:28 +00:00
br
6ac9bf43ac Correct RISC-V exception types. 2016-01-18 17:49:32 +00:00
br
8aa125d0c3 Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.

Reviewed by:	andrew, imp, kib
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D4554
2015-12-17 18:44:30 +00:00