Commit Graph

614 Commits

Author SHA1 Message Date
Ruslan Ermilov
934d7bccdb Renamed PCI_INTERFACE_XHCI to PCIP_SERIALBUS_USB_XHCI and moved it
to <dev/pci/pcireg.h>.

Reviewed by:	hselasky
MFC after:	3 days
2011-05-17 11:23:43 +00:00
Henrik Brix Andersen
adc38bf22f Allow direct children of PCI-ISA bridges to allocate resources from
the parent PCI bus.

Heavily inspired by jhb@ and a similar implementation present in
sys/dev/pci/vga_pci.c.

Reviewed by:	jhb
Approved by:	jhb
2011-05-13 15:06:35 +00:00
John Baldwin
83c41143ca Reimplement how PCI-PCI bridges manage their I/O windows. Previously the
driver would verify that requests for child devices were confined to any
existing I/O windows, but the driver relied on the firmware to initialize
the windows and would never grow the windows for new requests.  Now the
driver actively manages the I/O windows.

This is implemented by allocating a bus resource for each I/O window from
the parent PCI bus and suballocating that resource to child devices.  The
suballocations are managed by creating an rman for each I/O window.  The
suballocated resources are mapped by passing the bus_activate_resource()
call up to the parent PCI bus.  Windows are grown when needed by using
bus_adjust_resource() to adjust the resource allocated from the parent PCI
bus.  If the adjust request succeeds, the window is adjusted and the
suballocation request for the child device is retried.

When growing a window, the rman_first_free_region() and
rman_last_free_region() routines are used to determine if the front or
end of the existing I/O window is free.  From using that, the smallest
ranges that need to be added to either the front or back of the window
are computed.  The driver will first try to grow the window in whichever
direction requires the smallest growth first followed by the other
direction if that fails.

Subtractive bridges will first attempt to satisfy requests for child
resources from I/O windows (including attempts to grow the windows).  If
that fails, the request is passed up to the parent PCI bus directly
however.

The PCI-PCI bridge driver will try to use firmware-assigned ranges for
child BARs first and only allocate a "fresh" range if that specific range
cannot be accommodated in the I/O window.  This allows systems where the
firmware assigns resources during boot but later wipes the I/O windows
(some ACPI BIOSen are known to do this) to "rediscover" the original I/O
window ranges.

The ACPI Host-PCI bridge driver has been adjusted to correctly honor
hw.acpi.host_mem_start and the I/O port equivalent when a PCI-PCI bridge
makes a wildcard request for an I/O window range.

The new PCI-PCI bridge driver is only enabled if the NEW_PCIB kernel option
is enabled.  This is a transition aide to allow platforms that do not
yet support bus_activate_resource() and bus_adjust_resource() in their
Host-PCI bridge drivers (and possibly other drivers as needed) to use the
old driver for now.  Once all platforms support the new driver, the
kernel option and old driver will be removed.

PR:		kern/143874 kern/149306
Tested by:	mav
2011-05-03 17:37:24 +00:00
John Baldwin
d2c9344ff9 Add implementations of BUS_ADJUST_RESOURCE() to the PCI bus driver,
generic PCI-PCI bridge driver, x86 nexus driver, and x86 Host to PCI bridge
drivers.
2011-05-02 14:13:12 +00:00
John Baldwin
8adcbaed13 Only align MSI message groups based on the number of messages being
allocated, not the maximum number of messages the device supports.  The
spec only requires the former, and I believe I implemented the latter due
to misunderstanding an e-mail.  In particular, this fixes an issue where
having several devices that all support 16 messages can run out of
IDT vectors on x86 even though the driver only uses a single message.

Submitted by:	Bret Ketchum  bcketchum of gmail
MFC after:	1 week
2011-04-27 20:08:44 +00:00
John Baldwin
a90dd577e7 Explicitly track the state of all known BARs for each PCI device. The PCI
bus driver will now remember the size of a BAR obtained during the initial
bus scan and use that size when doing lazy resource allocation rather than
resizing the BAR.  The bus driver will now also report unallocated BARs to
userland for display by 'pciconf -lb'.  Psuedo-resources that are not BARs
(such as the implicit I/O port resources for master/slave ATA controllers)
will no longer be listed as BARs in 'pciconf -lb'.  During resume, BARs are
restored from their new saved state instead of having the raw registers
saved and restored across resume.  This also fixes restoring BARs at
unusual loactions if said BAR has been allocated by a driver.

Add a constant for the offset of the ROM BIOS BAR in PCI-PCI bridges and
properly handle ROM BIOS BARs in PCI-PCI bridges.  The PCI bus now also
properly handles the lack of a ROM BIOS BAR in a PCI-Cardbus bridge.

Tested by:	jkim
2011-03-31 13:22:12 +00:00
John Baldwin
3b0a4aef96 Do a sweep of the tree replacing calls to pci_find_extcap() with calls to
pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
John Baldwin
e786cbfdd2 Rename pci_find_extcap() to pci_find_cap(). PCI now uses the term
"extended capabilities" to refer to the new set of capability structures
starting at offset 0x100 in config space for PCI-express devices.  For now
both function names will still work.  I will merge this to older branches
to ease driver portability, but 9.0 will ship with a new pci_find_extcap()
function that locates extended capabilities instead.

Reviewed by:	imp
MFC after:	1 week
2011-03-22 12:05:49 +00:00
John Baldwin
54a03acb86 Partially revert previous change. Drop the quirk to disable MSI for HT
chipsets that do not have an HT slave at 0:0:0:0.  The Linux quirk is
actually specific to Nvidia chipsets and the check I had added was in
the wrong place.

Prodded by:	nathanw
2011-03-18 14:06:12 +00:00
John Baldwin
8081bab70b Fix a few issues with HyperTransport devices and MSI interrupts:
- Always enable the HyperTransport MSI mapping window for HyperTransport
  to PCI bridges (these show up as HyperTransport slave devices).
  The mapping windows in PCI-PCI bridges are enabled by existing code
  in the PCI-PCI bridge driver as MSI requests propagate up the device
  tree, but Host-PCI bridges don't really show up in that tree.
- If the PCI device at domain 0 bus 0 slot 0 function 0 is not a
  HyperTransport device, then blacklist MSI on any other HT devices in
  the system.  Linux has a similar quirk.

PR:		kern/155442
Tested by:	Zack Dannar  zdannar of gmail
MFC after:	1 week
2011-03-18 12:13:04 +00:00
John Baldwin
6e2b68aab6 Properly handle BARs bigger than 4G. The '1' was treated as an int
causing the size calculation to be truncated to the size of an int
(32-bits on all current architectures).

Submitted by:	Anish  akgupt3 of gmail
MFC after:	1 week
2011-02-23 12:58:50 +00:00
Marcel Moolenaar
bba39e1034 Use the preload_fetch_addr() and preload_fetch_size() convenience
functions to obtain the address and size of the PCI vendor data.

Sponsored by: Juniper Networks.
2011-02-13 19:26:51 +00:00
John Baldwin
da1781dd59 Don't whine about child drivers calling pci_enable_busmaster(). That is
perfectly normal.

MFC after:	1 week
2010-12-20 14:54:24 +00:00
John Baldwin
9d76324839 Add device IDs for two more ServerWorks Host-PCI bridges so that we can
read their starting PCI bus number for older systems that do not support
ACPI (or have a broken _BBN method).

PR:		kern/148108
MFC after:	1 week
2010-11-25 15:42:33 +00:00
Jung-uk Kim
f68ff88c87 Resume critical PCI devices (and their children) first, then everything else
later.  This give us better chance to catch device driver problems.
2010-11-22 21:58:00 +00:00
Nathan Whitehorn
495ed64c16 The EHCI_CAPLENGTH and EHCI_HCIVERSION registers are actually sub-registers
within the first 4 bytes of the EHCI memory space. For controllers that
use big-endian MMIO, reading them with 1- and 2-byte reads would then
return the wrong values. Instead, read the combined register with a 4-byte
read and mask out the interesting quantities.
2010-10-25 15:51:43 +00:00
John Baldwin
ba577448a2 - Add a new PCI quirk to whitelist an old chipset that doesn't support
PCI-express or PCI-X capabilities if we are running in a virtual machine.
- Whitelist the Intel 82440 chipset used by QEMU.

Tested by:	jfv
MFC after:	1 week
2010-10-22 11:42:02 +00:00
John Baldwin
fb2439a6f6 Clarify a misleading comment. The test in pci_reserve_map() was meant to
ignore BARs that are invalid due to having a size of zero, not to ignore
BARs with an existing base of zero.  While here, reorganize the code
slightly to make the intent clearer.

Reported by:	avg
MFC after:	1 week
2010-10-21 17:46:23 +00:00
Jung-uk Kim
d815d0abb7 Update PCI power management registers per PCI Bus Power Management Interface
Specification Rev. 1.2.  Rename pp_pcmcsr field of PM capabilities to pp_bse
to avoid further confusions and adjust some comments accordingly.  The real
PMCSR (Power Management Control/Status Register) is PCIR_POWER_STATUS and
it is actually BSE (PCI-to-PCI Bridge Support Extensions) register.
2010-10-20 23:41:16 +00:00
Jung-uk Kim
f3e0b10973 Introduce a new tunable 'hw.pci.do_power_suspend'. This tunable lets you
avoid PCI power state transition from D0 to D3 for suspending case.  Default
is 1 or enabled.
2010-10-20 16:47:09 +00:00
Jung-uk Kim
347263c935 Do not apply do_power_resume for suspending P2P bridge as we did in r214064. 2010-10-20 16:40:14 +00:00
Jung-uk Kim
6d018c85e1 Remove PCI header type 0 restriction from power state changes. PCI config.
registers for bridges are saved and restored since r200341.

OK'ed by:	imp, jhb
2010-10-19 17:15:22 +00:00
Jung-uk Kim
b56b75259b Do not apply do_power_resume for suspending case. When do_powerstate was
splitted into do_power_resume and do_power_nodriver, it became stale.
2010-10-19 17:05:51 +00:00
Jung-uk Kim
debfe32ccd Remove unnecessary castings and fix couple of style(9) nits. 2010-10-15 21:41:59 +00:00
Jung-uk Kim
6e877573df Move setting power state for children into a separate function as they were
essentially the same.  This also restores hw.pci.do_power_resume tunable,
which was broken since r211430.

Reviewed by:	jhb
2010-10-15 21:39:51 +00:00
John Baldwin
da6b22afaf - Rename the constant for the Master Data Parity Error flag in the
PCI status register to map its current name.
- Use PCIM_* rather than PCIR_* for constants for fields in various AER
  registers.  I got about half of them right in the previous commit.

MFC after:	1 week
2010-09-09 18:19:15 +00:00
John Baldwin
79c2de35b5 - Add register definitions related to extended capability IDs in
PCI-express.  I used PCIZ_* for ID constants (plain capability IDs use
  PCIY_*).
- Add register definitions for the Advanced Error Reporting, Virtual
  Channels, and Device Serial Number extended capabilities.
- Teach pciconf -c to list extended as well as plain capabilities.   Adds
  more detailed parsing for AER, VC, and device serial numbers.

MFC after:	2 weeks
2010-09-08 17:53:34 +00:00
John Baldwin
62508c531e Add a new method to the PCI bridge interface, PCIB_POWER_FOR_SLEEP(). This
method is used by the PCI bus driver to query the power management system
to determine the proper device state to be used for a device during suspend
and resume.  For the ACPI PCI bridge drivers this calls
acpi_device_pwr_for_sleep().  This removes ACPI-specific knowledge from
the PCI and PCI-PCI bridge drivers.

Reviewed by:	jkim
2010-08-17 15:44:52 +00:00
John Baldwin
7d23a9b3d5 - Retire acpi_pcib_resume(). It is has just been an alias for
bus_generic_resume() since the pci_link(4) driver was added.
- Change the ACPI PCI-PCI bridge driver to inherit most of its methods
  from the generic PCI-PCI bridge driver.  In particular, this will now
  restore PCI config registers for ACPI PCI-PCI bridges.

Tested by:	Oleg Sharoyko  osharoiko of gmail
2010-08-05 16:10:12 +00:00
Pyun YongHyeon
f39cf57f91 Consistently check header type after reading PCIR_HDRTYPE register.
While I'm here use defined macro instead of using magic numbers for
header type.

Reviewed by:	jhb
2010-07-29 20:42:38 +00:00
Neel Natu
762aad8142 Fix 'pciconf -a' by providing an implementation of PCIOCATTACHED.
Reviewed by:	imp
MFC after:	1 week
Pointed out by:	Heymian Wong (heymian at mit.alum.edu)
Sponsored by:	NetApp
2010-07-29 06:27:41 +00:00
Rafal Jaworowski
c5a514a756 Provide more defines for PCI-Express device ctrl. 2010-07-11 20:55:39 +00:00
Alexander Motin
93fc07b434 Virtualize pci_remap_msi_irq() call from general MSI code. It allows MSI
(FSB interrupts) to be used by non-PCI devices, such as HPET.
2010-06-14 07:10:37 +00:00
Alexander Motin
75f5385157 Honor hw.pci.do_power_nodriver on resume. Power-down devices without
driver attached.
2010-05-22 03:19:30 +00:00
Nathan Whitehorn
ca2c19312e Add support for the U4 PCI-Express bridge chipset used in late-generation
Powermac G5 systems. MSI and several other things are not presently
supported.

The U3/U4 internal device support portions of this change were contributed
by Andreas Tobler.

MFC after:	1 week
2010-05-16 15:18:25 +00:00
John Baldwin
5d82e6d067 Small whitespace fixes. 2010-03-11 15:25:47 +00:00
Alexander Motin
24d6a5ed27 Add pci_get|set_max_read_req() helper functions to control maximum PCIe
read request size.

Reviewed by:	jhb@
2010-02-05 17:18:48 +00:00
Pyun YongHyeon
bde52fe26d Add more bit definitions to PCI express device control and device
status register.

Reviewed by:	jhb
2010-02-01 20:50:49 +00:00
John Baldwin
af827f9642 Move the PCI-specific logic of removing a cardbus device into a
pci_delete_child() function called by the cardbus driver.  The new function
uses resource_list_unreserve() to release the BARs decoded by the device
being removed.

Reviewed by:	imp
Tested by:	brooks
2010-01-05 20:42:25 +00:00
John Baldwin
4e8790e943 Teach the PCI bus driver to handle PCIR_BIOS BARs properly and remove special
handling for the PCIR_BIOS decoding enable bit from the cardbus driver.
The PCIR_BIOS BAR does include type bits like other BARs.  Instead, it is
always a 32-bit non-prefetchable memory BAR where the low bit is used as a
flag to enable decoding.

Reviewed by:	imp
2009-12-30 20:47:14 +00:00
John Baldwin
1280c1198d Remove no longer used pci_release_resource(). 2009-12-30 19:46:09 +00:00
Jung-uk Kim
e36af2929a Implement a rudimentary suspend/resume methods for PCI P2P bridge.
Reviewed by:	jhb, imp
2009-12-10 01:01:53 +00:00
John Baldwin
42a346fa63 For some buses, devices may have active resources assigned even though they
are not allocated by the device driver.  These resources should still appear
allocated from the system's perspective so that their assigned ranges are
not reused by other resource requests.  The PCI bus driver has used a hack
to effect this for a while now where it uses rman_set_device() to assign
devices to the PCI bus when they are first encountered and later assigns
them to the actual device when a driver allocates a BAR.  A few downsides of
this approach is that it results in somewhat confusing devinfo -r output as
well as not being very easily portable to other bus drivers.

This commit adds generic support for "reserved" resources to the resource
list API used by many bus drivers to manage the resources of child devices.
A resource may be reserved via resource_list_reserve().  This will allocate
the resource from the bus' parent without activating it.
resource_list_alloc() recognizes an attempt to allocate a reserved resource.
When this happens it activates the resource (if requested) and then returns
the reserved resource.  Similarly, when a reserved resource is released via
resource_list_release(), it is deactivated (if it is active) and the
resource is then marked reserved again, but is left allocated from the
bus' parent.  To completely remove a reserved resource, a bus driver may
use resource_list_unreserve().  A bus driver may use resource_list_busy()
to determine if a reserved resource is allocated by a child device or if
it can be unreserved.

The PCI bus driver has been changed to use this framework instead of
abusing rman_set_device() to keep track of reserved vs allocated resources.

Submitted by:	imp (an older version many moons ago)
MFC after:	1 month
2009-12-09 21:52:53 +00:00
Andrew Thompson
e6af527c11 Disable interrupts after doing early takeover of the usb controller in case usb
isnt actually compiled in (or kldloaded) as the controller could cause spurious
interrupts.

Tested by:	Florian Smeets
2009-11-25 20:50:43 +00:00
Jung-uk Kim
bf71c25f87 - Partially revert hackish r198964 and r199002.
- Add a proxy driver vgapm to help vgapci to save/load VGA state.
- Move device_set_desc() to the right place while we are here.

Reviewed by:	jhb
2009-11-12 17:56:56 +00:00
Jung-uk Kim
b66e2b8e50 Remove duplicate suspend/resume code from vga_pci.c and let vga(4) register
itself to an associated PCI device if it exists.  It is little bit hackish
but it should fix build without frame buffer driver since r198964.
Fix some style(9) nits in vga_isa.c while we are here.
2009-11-06 20:32:26 +00:00
Jung-uk Kim
2259d74c68 Save/restore VGA state from vga_pci.c instead of relying on vga_isa.c.
It was not working because we were saving its state after the device was
powered down.  Simplify vesa_load_state() as the culprit is fixed now.
2009-11-05 22:58:50 +00:00
Marcel Moolenaar
d6eb44c8b0 BIOSes, buggy or otherwise, are i386 or amd64 specific.
Have the early USB takeover enabled for i386 and amd64
by default.
This also avoids a panic on PowerPC where the resource
isn't released properly and we find a busy resource
when the USB host controller wants to allocate it...
2009-10-23 22:53:01 +00:00
Jung-uk Kim
3219f535d9 Rewrite x86bios and update its dependent drivers.
- Do not map entire real mode memory (1MB).  Instead, we map IVT/BDA and
ROM area separately.  Most notably, ROM area is mapped as device memory
(uncacheable) as it should be.  User memory is dynamically allocated and
free'ed with contigmalloc(9) and contigfree(9).  Remove now redundant and
potentially dangerous x86bios_alloc.c.  If this emulator ever grows to
support non-PC hardware, we may implement it with rman(9) later.
- Move all host-specific initializations from x86emu_util.c to x86bios.c and
remove now unnecessary x86emu_util.c.  Currently, non-PC hardware is not
supported.  We may use bus_space(9) later when the KPI is fixed.
- Replace all bzero() calls for emulated registers with more obviously named
x86bios_init_regs().  This function also initializes DS and SS properly.
- Add x86bios_get_intr().  This function checks if the interrupt vector is
available for the platform.  It is not necessary for PC-compatible hardware
but it may be needed later. ;-)
- Do not try turning off monitor if DPMS does not support the state.
- Allocate stable memory for VESA OEM strings instead of just holding
pointers to them.  They may or may not be accessible always.  Fix a memory
leak of video mode table while I am here.
- Add (experimental) BIOS POST call for vesa(4).  This function calls VGA
BIOS POST code from the current VGA option ROM.  Some video controllers
cannot save and restore the state properly even if it is claimed to be
supported.  Usually the symptom is blank display after resuming from suspend
state.  If the video mode does not match the previous mode after restoring,
we try BIOS POST and force the known good initial state.  Some magic was
taken from NetBSD (and it was taken from vbetool, I believe.)
- Add a loader tunable for vgapci(4) to give a hint to dpms(4) and vesa(4)
to identify who owns the VESA BIOS.  This is very useful for multi-display
adapter setup.  By default, the POST video controller is automatically
probed and the tunable "hw.pci.default_vgapci_unit" is set to corresponding
vgapci unit number.  You may override it from loader but it is very unlikely
to be necessary.  Unfortunately only AGP/PCI/PCI-E controllers can be
matched because ISA controller does not have necessary device IDs.
- Fix a long standing bug in state save/restore function.  The state buffer
pointer should be ES:BX, not ES:DI according to VBE 3.0.  If it ever worked,
that's because BX was always zero. :-)
- Clean up register initializations more clearer per VBE 3.0.
- Fix a lot of style issues with vesa(4).
2009-10-19 20:58:10 +00:00
Andrew Thompson
1def609a63 Workaround buggy BIOS code in USB regard. By doing the BIOS to OS handover for
all host controllers at the same time, we avoid problems where the BIOS will
actually write to the USB registers of all the USB host controllers every time
we handover one of them, and consequently reset the OS programmed values.

Submitted by:	avg
Reviewed by:	jhb
2009-10-15 20:07:08 +00:00