I don't know what alternate universe I was inhabiting when I wrote it
originally, but apparently the basic workings of mathematics were different
than in this universe. I also can't explain how it ever worked, except "by
accident", because completely bogus values were being written into the
divisor register.
(1) The pmap argument passed to the function must be current pmap only.
(2) The process must be single threaded as the function is called either
when a process is exiting or from exec_new_vmspace().
Remove pmap_tlb_flush_ng() which is not used anywhere now.
Approved by: kib (mentor)
in pmap_remove_pages().
Some points were considered:
(1) There is no range TLB flush cp15 function.
(2) There is no target selection for hardware TLB flush broadcasting.
(3) Some memory ranges could be mapped sparsely.
(4) Some memory ranges could be quite large.
Tested by buildworld on RPi2 and Jetson TK1, i.e. 4 core platforms.
It turned out that the buildworld time is faster. On the other hand,
when the postponed TLB flush was also removed from pmap_remove_pages(),
the result was worse. But pmap_remove_pages() is called for removing
all user mapping from a process, thus it's quite expected.
Note that the postponed TLB flushes came here from i386 pmap where
hardware TLB flush broadcasting is not available.
Approved by: kib (mentor)
This fixes an issue observed on Cortex A7 (RPi2) and on Cortex A15
(Jetson TK1) causing various memory corruptions. It turned out that
even L2 page table with no valid mapping might be a subject of such
caching.
Note that not all platforms have intermediate TLB caching implemented.
An open question is if this fix is sufficient for all platforms with
this feature.
Approved by: kib (mentor)
These helper functions can be used to read in or write a buffer from or to
an arbitrary process' address space. Without them, this can only be done
using proc_rwmem(), which requires the caller to fill out a uio. This is
onerous and results in code duplication; the new functions provide a simpler
interface which is sufficient for most existing callers of proc_rwmem().
This change also adds a manual page for proc_rwmem() and the new functions.
Reviewed by: jhb, kib
Differential Revision: https://reviews.freebsd.org/D4245
clock_gettime(2) on ARMv7 and ARMv8 systems which have architectural
generic timer hardware. It is similar how the RDTSC timer is used in
userspace on x86.
Fix a permission problem where generic timer access from EL0 (or
userspace on v7) was not properly initialized on APs.
For ARMv7, mark the stack non-executable. The shared page is added for
all arms (including ARMv8 64bit), and the signal trampoline code is
moved to the page.
Reviewed by: andrew
Discussed with: emaste, mmel
Sponsored by: The FreeBSD Foundation
Differential revision: https://reviews.freebsd.org/D4209
Boundary Trace to assembly to reduce the overhead of these checks.
Submitted by: Howard Su <howard0su@gmail.com>
Relnotes: Yes
Differential Revision: https://reviews.freebsd.org/D4266
This fixes detection of root interrupt controller for cases,
when interrupt parent is not defined at all or it's not defined directly
in controller node.
Approved by: kib (mentor)
- add new TEX class for WT cacheable memory
- export new TEX class to kernel as VM_MEMATTR_WT attribute
- add new aliases VM_MEMATTR_WRITE_COMBINING and
VM_MEMATTR_WRITE_BACK, it's used in DRM code
Note:
Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs,
WT requests is treated as uncacheable.
Approved by: kib (mentor)
sysent.
sv_prepsyscall is unused.
sv_sigsize and sv_sigtbl translate signal number from the FreeBSD
namespace into the ABI domain. It is only utilized on i386 for iBCS2
binaries. The issue with this approach is that signals for iBCS2 were
delivered with the FreeBSD signal frame layout, which does not follow
iBCS2. The same note is true for any other potential user if
sv_sigtbl. In other words, if ABI needs signal number translation, it
really needs custom sv_sendsig method instead.
Sponsored by: The FreeBSD Foundation
so that code shared between imx5 and imx6 can work with OIDs under that node.
Add last_reset_status (integer) and last_reset_reason (string) OIDs that
provide info about the last chip reset (power-on, software reset, watchdog
timeout).
Replace tlb_flush_local() by tlb_flush() as even not global mappings
could be fetched to TLB(s) on other cores by speculative table walk.
From OS point of view, it was not a problem as either such mappings
were not used anymore or they were flushed from TLB(s) when reused.
However, from hardware point of view, it was a problem. Not flushed
mappings could be a target for speculative reads or prefetches (which
might be quite aggresive on ARM cores). As speculative read can fill
cacheline, it can cause a real problem, when physical page is reused,
but mapped with different memory attributes.
Anyhow, it's good to have only valid mappings in TLB(s).
Approved by: kib (mentor)
of the SRS (software reset) bit in the watchdog control register. Despite
what the manual seems to imply, this bit DOES trigger an immediate reset, as
opposed to simply flagging the type of reset as software-triggered.
created for bus_dma_tag_t tag, bounce pages should be allocated
only if needed.
Before the fix, they were allocated always if BUS_DMA_COULD_BOUNCE flag
was set but BUS_DMA_MIN_ALLOC_COMP not. As bounce pages are never freed,
it could cause memory exhaustion when a lot of such tags together with
their maps were created.
Note that there could be more maps in one tag by current design.
However BUS_DMA_MIN_ALLOC_COMP flag is tag's flag. It's set after
bounce pages are allocated. Thus, they are allocated only for first
tag's map which needs them.
Approved by: kib (mentor)
Drivers can request DMA to buffers that are not in memory represented
in the vm page arrays. Because of this, store KVA of already mapped
buffer to synclist and use it in dma_dcache_sync().
Reviewed by: jah
Approved by: kib (mentor)
Differential Revision: https://reviews.freebsd.org/D4120
This structure must be binary compatible regardless of PMAP
version being used. Create reserved section for NEW_PMAP to
make other variables be placed exactly in the same memory
addresses. This fixes kgdb/gdb behavoiur, which uses pcb.h stuctures.
The NEW_PMAP is kernel flag, so it does not propagate to the buildworld,
what makes the tools using pcb.h unable to parse PCB data.
Reviewed by: mmel, kib
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4011
Use proper size of exynos_ehci_softc, not the generic one.
Reviewed by: andrew
Submitted by: Wojciech Macek <wma@semihalf.com>
Obtained from: Semihalf
Sponsored by: Juniper Networks Inc.
Differential Revision: https://reviews.freebsd.org/D4189
Zybo needs its own DTB and has a different PHY, so add it to
the base kernel. Details on building bootable SD images at
http://www.thomasskibo.com/zedbsd/
Submitted By: Thomas Skibo
