> Description of fields to fill in above: 76 columns --|
> PR: If a GNATS PR is affected by the change.
> Submitted by: If someone else sent in the change.
> Reviewed by: If someone else reviewed your modification.
> Approved by: If you needed approval for this commit.
> Obtained from: If the change is from a third party.
> MFC after: N [day[s]|week[s]|month[s]]. Request a reminder email.
> Security: Vulnerability reference (one per line) or description.
> Empty fields above will be automatically removed.
M rmi/xls_ehci.c
M rmi/clock.h
M rmi/xlr_pci.c
M rmi/perfmon.h
M rmi/uart_bus_xlr_iodi.c
M rmi/perfmon_percpu.c
M rmi/iodi.c
M rmi/pcibus.c
M rmi/perfmon_kern.c
M rmi/perfmon_xlrconfig.h
M rmi/pcibus.h
M rmi/tick.c
M rmi/xlr_boot1_console.c
M rmi/debug.h
M rmi/uart_cpu_mips_xlr.c
M rmi/xlrconfig.h
M rmi/interrupt.h
M rmi/xlr_i2c.c
M rmi/shared_structs.h
M rmi/msgring.c
M rmi/iomap.h
M rmi/ehcireg.h
M rmi/msgring.h
M rmi/shared_structs_func.h
M rmi/on_chip.c
M rmi/pic.h
M rmi/xlr_machdep.c
M rmi/ehcivar.h
M rmi/board.c
M rmi/clock.c
M rmi/shared_structs_offsets.h
M rmi/perfmon_utils.h
M rmi/board.h
M rmi/msgring_xls.c
M rmi/intr_machdep.c
addresses and could modify areas of memory that share the same cache
line at the beginning and at the ending of the buffer. In order to
prevent a data loss we save these chunks in temporary buffer before
invalidation and restore them afer it.
Idea suggested by: cognet
calls us to fix it, we then issue a read for a full sector and then copy in/out
the payload. This will happen if Redboot is compiled with
CYGSEM_REDBOOT_FLASH_COMBINED_FIS_AND_CONFIG.
The "_MTC0 v0, COP_0_TLB_HI" is actually incorrect because v0 has not been
initialized at that point. It worked correctly because we subsequently
did the right thing and initialized TLB_HI correctly.
The "li v0, MIPS_KSEG0_START" is redundant because we do exactly the same
thing 2 instructions down.
Approved by: imp (mentor)
SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE
Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.
Approved by: imp (mentor)
in cpu_switch and use it in stack_trace function later. pcb_regs contains
state of the process stored by exception handler and therefor is not
valid for sleeping processes.
Context info could be obtained from other sources (see below) no only from
td_pcb field
- Do not show a0..a3 values unless they're obtained from the stack. These
are only confirmed values.
- Fix bt command in DDB. Previous implementation used thread's trapframe
structure as a source info for trace unwinding, but this structure
is filled only when exception occurs. Valid register values for sleeping
processes are in pcb_context array. For curthread use pc/sp/ra for current
frame
compile and many of them may disappear. For example
the xlr_boot1_console.c is old code that is ifdef'd out.
I will clean these sorts of things up as I make progress
on the port. So far the only thing I have I think straightened
out is the bits around the interupt handling... and hey that
may be broke ;-)
that will need working on to fit from 6.x -> head. But first
I must get the base to compile (wanted to get as much in the tree
as I could before my flight to India).
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
intr_machdep.c. This allows us to have an architecture dependant intr_machdep.c
(which we will need for RMI) in the machine specific directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
may need to look at finding a better place to put this. But first I want to
get this thing compiling.
interrupted and after re-run new files were not added to repo though
respective revisions were marked as merged. This commit presents latest
versions of these files.
