so that the data is less likely to be inconsistent if SYSCTL_OUT() blocks.
If the data is large, wire the output buffer instead.
This is somewhat less than optimal, since the handler could skip the copy
if it knew that the data was static.
If the data is dynamic, we are still not guaranteed to get a consistent
copy since another processor could change the data while the copy is in
progress because the data is not locked. This problem could be solved if
the generic handlers had the ability to grab the proper lock before the
copy and release it afterwards.
This may duplicate work done in other sysctl handlers in the kernel which
also copy the data, possibly while a lock is held, before calling they call
a generic handler to output the data. These handlers should probably call
SYSCTL_OUT() directly.
SYSCTL_OUT() from blocking while locks are held. This should
only be done when it would be inconvenient to make a temporary copy of
the data and defer calling SYSCTL_OUT() until after the locks are
released.
userland for libc/gmon to compile, so the typedef in <machine/types.h>
isn't good enough. This is really ugly since we end up with the
actual value which uintfptr_t is typedef'd from, in multiple places.
This is bug for bug compatible with the other FreeBSD architectures.
Noticed by: sparc64 tinderbox
ruleset. If we do, that means there's a ruleset loop (10 includes 20
include 30 includes 10), which will quickly cause a double fault due
to stack overflow (since "include" is implemented by recursion).
(Previously, we only checked that X didn't include X.)
not responding) then drop any data on the outgoing queue in
soisdisconnected because there is no way to get it to its destination
any longer.
The only objection to this patch I got on -net was from Terry, who
wasn't sure that the condition in question could arise, so I provided
some example code.
basically maps all of physical memory 1:1 to a range of virtual addresses
outside of normal kva. The advantage of doing this instead of accessing
phsyical addresses directly is that memory accesses will go through the
data cache, and will participate in the normal cache coherency algorithm
for invalidating lines in our own and in other cpus' data caches. So
we don't have to flush the cache manually or send IPIs to do so on other
cpus. Also, since the mappings never change, we don't have to flush them
from the tlb manually.
This makes pmap_copy_page and pmap_zero_page MP safe, allowing the idle
zero proc to run outside of giant.
Inspired by: ia64
implementation. This flag will indicate that the security label
in the vnode is currently valid, and therefore doesn't need to
be refreshed before an access control decision can be made. Most
file systems (or stdvops) will set this flag after they load the
MAC label from disk the first time to prevent redundant disk I/O;
some file synthetic file systems (procfs, for example) may not.
Obtained from: TrustedBSD Project
Sponsored by: DARPA, NAI Labs
MAC support will be merged into the main tree over the next week in
reasonable size chunks; much more to follow.
Obtained from: TrustedBSD Project
Sponsored by: DARPA, NAI Labs
during execve() to use a 'credential_changing' variable. This makes it
easier to have outstanding patchsets against this code, as well as to
add conditionally defined clauses.
Obtained from: TrustedBSD Project
Sponsored by: DARPA, NAI Labs
since it breaks mtx_owned() on spin mutexes when used outside of
mtx_assert(). Unfortunately we currently use it in the i386 MD code
and in the sio(4) driver.
Reported by: bde
o reduce the extra-long ID names.
o TI-1510, 1520 and 4510 support.
o MFUNC is the name of the register on TI 1200 and newer chips (except
125x and 1450). Initialize it in the func routine, but only
if NO_MFUNC isn't set.
o better comments about above workaround
o register definitions for MFUNC.
o move zoom video disable to a better place.
o Rename the insanely long PCIC bridge ids.
o Add my copyright to pccbb.c
o Add support for the TI-1510, TI-1520 and TI-4510 series of upcoming
bridges.
o Init MFUNC if it is zero and the TI part has a MFUNC register
at offset 0x8c (1030, 1130 and 1131 don't have anything there, the
1250,1251,1251B and 1450 have a different thing there. The rest
have it. TI is likely to only do MFUNC from now on. The IRQMUX
in the 1250 series of chips needs no tweaks.
o Adjust to new exca interface.
o Add comments about TI chips that I learned in talking to an
engineer at TI.
o Add register definitions for MFUNC.
o Create CB_TI125X chipset type.
o Protect .h against multiple includes.
o eliminate the pointers to the read/write routines. The
bus_space_read routines can cope since we have the offset
field.
o Print a warning if the requested map address is > 16M and
your chipset doesn't support the extended ExCA registers.
