-DBKTR_NEW_MSP34XX_DRIVER and -Wformat-security.
This also allows to eliminates a superfluous malloc/snprintf/free on
intermediate buffer.
PR: kern/175546
MFC after: 1 week
The NTB allows you to connect two systems with this device using a PCI-e
link. The driver is made of two modules:
- ntb_hw which is a basic hardware abstraction layer for the device.
- if_ntb which implements the ntb network device and the communication
protocol.
The driver is limited at the moment to CPU memcpy instead of using DMA, and
only Back-to-Back mode is supported. Also the network device isn't full
featured yet. These changes will be coming soon. The DMA change will also
bring in the ioat driver from the project branch it is on now.
This is an initial port of the GPL/BSD Linux driver contributed by Jon Mason
from Intel. Any bugs are my contributions.
Sponsored by: Intel
Reviewed by: jimharris, joel (man page only)
Approved by: jimharris (mentor)
* That lock isn't actually held during reset - just the whole TX/RX path
is paused. So, remove the assertion.
* Log the TX queue status - how many hardware frames are active in the
MAC and whether the queue is active.
/home/sbruno/bsd/head/sys/dev/hptrr/hptrr_osm_bsd.c:178:66: warning: for loop has empty body [-Wempty-body]
for (order=0, size=PAGE_SIZE; size<f->size; order++, size<<=1) ;
^
/home/sbruno/bsd/head/sys/dev/hptrr/hptrr_osm_bsd.c:178:66: note: put the semicolon on a separate line to silence this warning
Obtained from: Yahoo! Inc.
MFC after: 2 weeks
OpenCISS states that if the value is 0, then the driver should try a value
of 31. That's just silly. Set to 17 so that the subtraction for maxio
becomes 16 and aligns nicely.
Reviewed by: scottl
Obtained from: Yahoo! Inc.
MFC after: 2 weeks
Communication on src-commiters, Sat, 27 Apr 2013 22:09:06 -0700,
Subject was: "Re: svn commit: r249997"
As I'm here, fix the style main block comments in files' headers.
If max_sg_length is 0, then we default to 16
If max_sg_length is less than CISS_MAX_SG_ELEMENTS, then
we will set round the value of max_sg_length to the nearest
power of 2 and use it to align maxio.
Else, we will use CISS_MAX_SG_ELEMENTS for our calculations.
Thanks to scottl for working me through the history and providing
the basis for this patch.
Submitted by: scott
Obtained from: Yahoo! Inc.
MFC after: 2 weeks
and tuned value, we would advertise the unsupported value to CAM and it would
merrily destroy the controller with way too many IO operations.
This manifests itself in a Zero Memory RAID configuration for a P410 and
possibly other controllers.
Obtained from: Yahoo! Inc.
MFC after: 2 weeks
that uses non-ISA IRQs but use a plain IRQ resource in _CRS. However,
a non-ISA IRQ can't fit into a plain IRQ resource. If we encounter a
link like this, build the resource buffer from _PRS instead of _CRS.
- Set the correct size of the end tag in a resource buffer.
Tested by: Benjamin Lee <ben@b1c1l1.com>
MFC after: 2 weeks
than VLAN groups.
Some chips (eg this rtl8366rb) has a VLAN group per port - you first
define a set of VLANs in a vlan group, then you assign a VLAN group
to a port.
Other chips (eg the AR8xxx switch chips) have a VLAN ID array per
port - there's no group per se, just a list of vlans that can be
configured.
So for now, the switch API will use the latter and rely on drivers
doing the heavy lifting if one wishes to use the VLAN group method.
Maybe later on both can be supported.
PR: kern/177878
PR: kern/177873
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
Reviewed by: ray
the pause/resume code to not be called completely symmetrically.
I'll chase down the root cause of that soon; this at least works around
the bug and tells me when it happens.
is compiled in or not.
This fixes issues with people running -HEAD but who build modules
without doing a "make buildkernel KERNCONF=XXX", thus picking up
opt_*.h. The resulting module wouldn't have 11n enabled and the
chainmask configuration would just be plain wrong.
This is intended to be used as a stop-gap for switch devices
which expose multiple ethernet PHYs but we don't have a driver
for - here, etherswitchcfg and the general switch configuration
API can be used to interface to said PHYs.
Submitted by: Luiz Otavio O Souza <loos.br@gmail.com>
