146 Commits

Author SHA1 Message Date
loos
48a4e7ada2 Add support for the Marvell 88E6190 11 ports switch.
With more ports, some of the registers are shifted a bit to accommodate.

This switch also adds two high speed Serdes/SGMII interfaces (2.5 Gb/s).

Sponsored by:	Rubicon Communications, LLC (Netgate)
2019-07-01 13:41:37 +00:00
loos
0d3e1bbc17 Add the 802.1q support for the Marvell e6000 series of ethernet switches.
Tested on:	espressobin, Clearfog, SG-3100 and others
Sponsored by:	Rubicon Communications, LLC (Netgate)
2019-06-28 22:19:50 +00:00
loos
2817d8424f Add the 'drop tagged' flag support for ethernet switch ports.
This is intended to drop all 802.1q tagged packets on a port.

Sponsored by:	 Rubicon Communications, LLC (Netgate)
2019-06-28 22:12:43 +00:00
loos
aa28c8b916 Do not overwrite the RGMII bits in the CPU port register of Switch.
Fixes the network on Espressobin.

The GENERIC kernel now boots over NFS.

Sponsored by:	Rubicon Communications, LLC (Netgate)
2019-06-06 21:25:46 +00:00
mw
0e7675604a Update mvneta/e6000sw for new DSA Device Tree Bindings
In the latest Linux kernel revisions the DSA (Distributed
Switch Architecture) device tree binding was changed.
Instead of the top level dsa@ node, the switch and its
ports is represented as a child node of the mdio bus.
With that other modifications were added, such as
relation with the ethernet port of the SoC. Adjust
e6000sw etherswitch and mvneta drivers to that.

Tested on Armada 3720 EspressoBin and Armada 388 Clearfog Pro boards.

Submitted by: Bert JW Regeer <xistence@0x58.com>
Reviewed by: manu
Differential Revision: https://reviews.freebsd.org/D19036
2019-03-23 02:48:47 +00:00
mw
879cf7c79f Improve detection of addressing mode in e6000sw
Some devices cannot rely on the switch MDIO address passed in the DTB
for specifying single/multi-chip addressing mode. Introduce new property
"single-chip-addressing" which added to DTS will force single-chip mode.

Submitted by: Michal Mazur <mkm@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Differential Revision: https://reviews.freebsd.org/D14800
2018-04-10 08:35:43 +00:00
gonzo
1252c9346c Clean up OF_getprop_alloc API
OF_getprop_alloc takes element size argument and returns number of
elements in the property. There are valid use cases for such behavior
but mostly API consumers pass 1 as element size to get string
properties. What API users would expect from OF_getprop_alloc is to be
a combination of malloc + OF_getprop with the same semantic of return
value. This patch modifies API signature to match these expectations.

For the valid use cases with element size != 1 and to reduce
modification scope new OF_getprop_alloc_multi function has been
introduced that behaves the same way OF_getprop_alloc behaved prior to
this patch.

Reviewed by:	ian, manu
Differential Revision:	https://reviews.freebsd.org/D14850
2018-04-08 22:59:34 +00:00
adrian
2e003caf91 [arswitch] Implement the switch MAC address fetch API.
The placeholders are here for some future "set" MAC address API.

Tested:

* AR9340 switch
* AR8327 switch
2018-02-06 08:35:49 +00:00
adrian
0b160bb40e [etherswitch] add initial support for potentially configuring and fetching the switch MAC address.
Switches that originate their own frames (eg obvious ones like Pause frames)
need a MAC address to use to send those frames from.

This API will hopefully begin to allow that to be configurable.
2018-02-06 08:34:50 +00:00
adrian
412ccaa7d2 [arswitch] disable ARP copy-to-CPU port for AR9340 for now.
I'll have to go double check to see if it does indeed pass ARP frames between
switch ports with this disabled, but it seems required for the CPU port to see
ARP traffic.

I'll dig into this some more.
2018-02-05 20:37:29 +00:00
adrian
2b4040c4a4 [arswitch] fix build breakage.
Apparently the last time I checked building this it didn't pick up that the
header had changed.
2018-02-05 20:30:53 +00:00
adrian
3dd199ff91 [arswitch] Enable ATU dump support for the AR9340.
This indeed uses the same registers as the AR8216 and later chips.

There seems to be an issue with ARP requests being sent out from the CPU
through this switch here, so figuring that out is next.  Learning works fine on
the AR8327 ethernet switch on the /other/ gigabit ethernet port, so I don't
think it's the network stack or ethernet driver.

Tested:

* DB120 - AR9340 SOC + ethernet switch (and other bits.)
2018-02-05 07:05:28 +00:00
adrian
397201d265 [arswitch] fix mac address field definition.
Whilst here, add some further fields for future experimenting.

Tested:

* AR9340 switch
* AR9330 switch
* AR7240 switch
2018-02-05 07:03:45 +00:00
adrian
2ab6758d59 [arswitch] Break out of the loop upon any error, not just -1.
This fixes the AR9340 "unimplemented" thingy for now.
2018-02-05 05:51:37 +00:00
adrian
9164f1b780 [arswitch] fix up issues on the AR8327.
This correctly dumps the ethernet bridge contents on an AR8327 switch.

Tested:

* AP135 - QCA9550 + AR8327 ethernet switch:

# etherswitchcfg atu dump
 [0] c0:3f:d5:7e:6f:45: portmask 0x00000004
 [1] f6:b6:03:96:1e:ba: portmask 0x00000004
 [2] 00:03:7f:11:38:4f: portmask 0x00000040
# arp -na
? (192.168.3.170) at 00:03:7f:11:38:4f on arge0 permanent [ethernet]
? (192.168.3.12) at c0:3f:d5:7e:6f:45 on arge0 expires in 1188 seconds [ethernet]
? (192.168.3.1) at f6:b6:03:96:1e:ba on arge0 expires in 1186 seconds [ethernet]
2018-02-04 08:22:11 +00:00
adrian
3545b68be5 [arswitch] add initial functionality for AR8327 ATU management.
* Add the bulk of the ATU table read function
* Correct how the ATU function and WAIT bits work

TODO:

* more testing, figure out how the multi-vlan table stuff works and push that
  up to userspace
2018-02-03 00:59:08 +00:00
adrian
38c3f57881 [arswitch] Stub out the ATU table dump in AR9340 switches until I implement
this.
2018-02-02 22:08:03 +00:00
adrian
144a3ee3a5 [arswitch] begin tidying up the learning and ATU management, introduce ATU APIs.
* Refactor the initial learning configuration (port learning, address expiry,
  handling address moving between ports, etc, etc) into a separate HAL routine
* and ensure that it's consistent between switch chips - the AR8216,8316,724x,9331
  SoCs all share the same switch code.
* .. the AR8327 needs doing - the defaults seem OK for now
* .. the AR9340 is different but it's also programmed now.

* Add support for flushing a single port worth of ATU entries
* Add support for fetching the ATU table from AR8216 and derived chips

Tested:

* AR9344, Carambola 2

TODO:

* Further testing on other chips
* Add AR9340 support
* Add AR8327 support
2018-02-02 22:05:36 +00:00
adrian
a07554bea5 [etherswitch] add the first pass of a simple API to flush and fetch the L2 address table from the ethernet switch.
This stuff may be a bit fluid during this -HEAD cycle as various other
switch features are added, but the current stuff is enough to drive
initial development and features on the atheros range of integrated
and external switches.

* add a method to flush the whole address table;
* add a method to flush all addresses on a given port;
* add a method to download the address table;
* .. and then a method to fetch entries from the address table.

The table fetch/read methods pass through to the drivers for now since
the drivers may implement different ways of fetching/caching the address
table data.  The atheros devices for example fetch the table by
iterating over the table through a set of registers and so you need
to keep that locked whilst you iterate otherwise you may have the table
flushed half way by a port status change.

This is a no-op until the userland and arswitch code shows up.
2018-02-02 02:05:14 +00:00
adrian
12318046d5 [arswitch] Fix ATU programming on the AR8327 switch.
Doing a flush actually requires setting this bit.
2018-01-31 07:37:33 +00:00
adrian
d15af82b1a [arswitch] Fix ATU flushing on AR8216/AR8316 and most of the later chips.
The switch hardware requires this bit to be set in order to kick start the
actual ATU update.  This was being masked on some chips by the learning
programming (what to do when a MAC address moves, hash table collision, etc)
which is currently inconsistent between chips.

Tested:

* AR9344 SoC (AR7240 style switch internal)
2018-01-31 07:36:51 +00:00
adrian
b36494644e [arswitch] add a new debug section for upcoming address table management. 2018-01-31 07:20:34 +00:00
mizhka
ceb9715f37 [etherswitch] fix LINT build for rtl8366rb
Build with rtl8366rb has been broken due to incorrect retrieval of pointer
to device_t.

Reported by:	lwhsu
Differential Revision:	https://reviews.freebsd.org/D14044
2018-01-25 05:48:42 +00:00
mizhka
447acd1dc7 [etherswitch] check if_alloc returns NULL
This patch is cosmetic. It checks if allocation of ifnet structure failed.
It's better to have this check rather than assume positive scenario.

Submitted by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
Reported by:	Dmitry Luhtionov <dmitryluhtionov@gmail.com>
2018-01-24 21:33:18 +00:00
pfg
1537078d8f sys/dev: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 2-Clause license, however the tool I
was using misidentified many licenses so this was mostly a manual - error
prone - task.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.
2017-11-27 14:52:40 +00:00
loos
555ebaa3dd Fix the port vlan support in e6000 based switches.
Reduce the use of local copies of switch register data.

The switch now works with the upstream dsa node (i.e. the upstream DTS).

Tested on:	ClearFog Pro (88E6176), SG-3100 (88E6141)
Sponsored by:	Rubicon Communications, LLC (Netgate)
2017-07-27 02:38:53 +00:00
loos
3ba75ba1dd Add support to 2.5G uplink for the MV88E6141 and MV88E6341 switches.
Force the switch port settings for fixed media types.

Tested with:	88E6176, 88E6141
Sponsored by:	Rubicon Communications, LLC (Netgate)
2017-06-20 18:11:23 +00:00
zbb
de899400f8 Prevent multiple lock initialization in e6000sw probe
r319886 ("Add the initial support for the Marvell 88E6141
and 88E6341 switches.") unveiled a problem with possible
multiple lock creation. Move its initialization
to the driver attach and for obtaining the switch ID
create a temprorary one, which is immediately destroyed
after the check.

Submitted by: Zbigniew Bodek <zbb@semihalf.com>
	      Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
2017-06-13 18:35:14 +00:00
loos
c91f28aeed Add the initial support for the Marvell 88E6141 and 88E6341 switches.
Right now the driver only supports port VLANs, so make sure
etherswitch_getinfo() return the proper switch capabilities.

Handle the cases where not all ports are in use (that will also require
etherswitch cooperation).

Sponsored by:	Rubicon Communications, LLC (Netgate)
2017-06-13 00:42:23 +00:00
loos
0241533b04 Remove an unnecessary variable from the switch softc structure and make the
functions that are used as booleans return real boolean values.

Sponsored by:	Rubicon Communications, LLC (Netgate)
2017-06-09 20:38:18 +00:00
loos
228e64ca6d style(9) fixes, remove unnecessary headers, remove duplicate #defines and
in some cases, shuffle the code around to simplify locking.

No functional changes.

Sponsored by:	Rubicon Communications, LLC (Netgate)
2017-06-02 15:12:32 +00:00
mizhka
5fe5b73211 [etherswitch] [rtl8366] add phy4cpu setting and support mdioproxy
Tested on WZR-HP-G301NH(RTL8366RB) and WZR-HP-G300NH(RTL8366SR).

Submitted by:   Hiroki Mori <yamori813@yahoo.co.jp>
Differential Revision:	https://reviews.freebsd.org/D10740
2017-05-28 12:14:33 +00:00
adrian
ec4145b57e [arswitch] add phy debugging to the internal PHY read/write functions. 2017-05-23 03:48:42 +00:00
wma
63843c9be4 Poll PHY status using internal e6000sw registers
e6000sw family automatically reflects PHY status in each port's registers.
Therefore it is not necessary to do a full PHY polling squence, which
results in much quicker operation and much less significant usage of
the SMI bus.

Care must be taken that the resulting ifmedia_active is identical to
what the PHY will compute, or gratuitous link status changes will
occur whenever the PHYs update function is called.

This patch implements above improvement. On the occasion set a pointer to
the proc structure to be part of software context instead of being
a global variable.

Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10714
2017-05-19 08:24:23 +00:00
wma
b854df5591 Improve busy-wait loop during switch phy access in e6000sw
Hitherto implementation of PHY polling resulted in a risk of an
endless loop and very high occupation of the SMI bus. Improve the
operation by limiting the polling tries and adding sleepable
pause.

Submitted by: Marcin Wojtas <mw@semihalf.com>
Obtained from: Semihalf
Sponsored by: Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10713
2017-05-19 08:16:47 +00:00
zbb
13060c90f9 Add missing unlock in e6000sw driver
This patch adds missing unlock on attach failure.

Submitted by:  Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by:  Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10712
2017-05-17 15:59:45 +00:00
zbb
9701ccf52d Fix broken malloc in e6000sw
Malloc should always return something when M_WAITOK flag is used,
but keep this code and change flag to M_NOWAIT as it is under a lock
(allows for possible future change). Free ifnet structure to avoid
memory leak on failure.

Submitted by:  Zbigniew Bodek <zbb@semihalf.com>
Obtained from: Semihalf
Sponsored by:  Stormshield
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10711
2017-05-17 15:58:39 +00:00
adrian
636af1cddc [etherswitch] [e6000sw] fix compile issue under clang/arm
Submitted by:	Hiroki Mori <yamori813@yahoo.co.jp>
Approved by:	mizhka
Differential Revision:	https://reviews.freebsd.org/D10563
2017-05-06 06:07:44 +00:00
adrian
38ede6e193 [ip17x] [etherswitch] fdt away and mii hang workaround on ip17x
Add workaround mii access because of rt1310 is hang up on etherswitch mii poll.
And FDT away on arm platform.

Tested:

* wzr2-g300n

Submitted by:	Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by:	mizhka
Differential Revision:	https://reviews.freebsd.org/D10295
2017-05-06 05:53:42 +00:00
adrian
2bbd95abf8 [infineon] [etherswitch] no hardcode tagging port setting at amd6996fc
Tagging port can set by etherswitchcfg command.

Tested:

* on Netgear_WGR614Cv7

Submitted by:	Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by:	mizhka
2017-05-06 05:50:07 +00:00
loos
b0b3a75688 When the switch is set to operate in the Multi Chip Addressing Mode we
cannot access the GLOBAL2 register directly.

Despite the comment in code (which was misleading), the indirect access is
only used to read the switch CONFIG data from the scrap register and not
for the GLOBAL2 access.

Use the dsa data to define when the switch is in the Multi Chip Addressing
Mode (a even address different than zero).

While here fix a typo.

Sponsored by:	Rubicon Communications, LLC (Netgate)
2017-04-30 07:51:31 +00:00
mizhka
1621d23268 [etherswitch] add support for Marvell 88E6065 ethernet switch incl. 802.1q
This patch brings 802.1q support for Marvell 88E606x ethernet switches.
Test is done on 88E6065 chip (Aterm WR1200).

Submitted by:	Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by:	mizhka
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D10144
2017-03-27 19:06:29 +00:00
sgalabov
23c80c3239 etherswitch: Fix RT305x vlan group operation
Fix an issue which prevents proper operation (addition/removal of members)
of RT305x vlan groups.

Tested by:	yamori813@yahoo.co.jp

Submitted by:	yamori813@yahoo.co.jp (initial version)
Reviewed by:	adrian
Differential Revision:	https://reviews.freebsd.org/D9607
2017-02-20 08:10:41 +00:00
kp
bf7a58e32f arswitch: Ensure the lock is always held when calling arswitch_modifyreg()
arswitch_setled() and a number of _global_setup functions did not acquire the
lock before calling arswitch_modifyreg(). With WITNESS enabled this would
instantly panic.

Discovered on a TPLink-3600:
("panic: mutex arswitch not owned at sys/dev/etherswitch/arswitch/arswitch_reg.c:236")

Reviewed by:	adrian, kan
Differential Revision:	https://reviews.freebsd.org/D9187
2017-01-15 10:21:25 +00:00
mizhka
e8a7210247 [etherswitch] Support Micrel KSZ8995MA switch chip
This is Micrel KSZ8995MA driver code. KSZ8995MA uses SPI bus to control.
This code is written & tested on @SRCHACK's ksz8995ma board and FON2100
with gpiospi.
etherswitchcfg support commands: addtag, ingress, striptag, dropuntagged.

Submitted by:	Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by:	mizhka, adrian
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D8790
2017-01-14 23:24:50 +00:00
loos
5ff8fca605 Convert etherswitch to use the make_dev_s(9) KPI. This fix a possible race
where si_drv1 can be accessed before it gets set.

MFC after:	3 days
Suggested by:	kib
Sponsored by:	Rubicon Communications, LLC (Netgate)
2017-01-08 20:37:41 +00:00
zbb
33ec321971 Improve ports handling in e6000sw driver
- recognize ports and vlangroups based on DTS file
- support multi-chip addresing mode (required in upcoming
  Armada-388-Clearfog support)
- refactor attachment function

Each port in 'dsa' node should have 'vlangroup' property. Otherwise,
e6000sw will fail to attach.

Submitted by:	Bartosz Szczepanek <bsz@semihalf.com>
		Konrad Adamczyk <ka@semihalf.com>
Obtained from:	Semihalf
Sponsored by:	Stormshield
Differential revision: https://reviews.freebsd.org/D7328
2017-01-05 17:08:10 +00:00
loos
d326b0be0e Allow simultaneous access to switch device, there is no reason to prevent
it.

Remove bogus wrappers and use the kernel defaults.

While here, use DEVMETHOD_END.

Obtained from:	pfSense
MFC after:	2 weeks
Sponsored by:	Rubicon Communications, LLC (Netgate)
2016-12-03 01:55:38 +00:00
mizhka
98f1e47fee [etherswitch] add ukswitch hint that is phy offset at mdio register
This patch allows to specify PHY register offset for ukswitch. For instance,
switch MAICREL KS8995XA connected via MDIO to SoC, but PHY register starts
at 1. So hint for this case is: hint.ukswitch.0.phyoffset=1

No change/effect if hint is not set.

Submitted by:	Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by:	adrian, mizhka
Approved by:	adrian(mentor)
Differential Revision:	https://reviews.freebsd.org/D8584
2016-11-21 19:26:22 +00:00
mizhka
8889f6fadf [etherswitch] add infineon adm6996fc support on etherswitch
This is Infineon ADM6996FC/M/MX driver code on etherswitch framework.
Support PORT and DOT1Q VLAN.
This code suppose ADM6996FC SDC/SDIO connect to SOC network interface
MDC/MDIO.
This code tested on Netgear WGR614Cv7.

Submitted by:	Hiroki Mori <yamori813@yahoo.co.jp>
Reviewed by:	adrian, mizhka
Approved by:	adrian(mentor)
Differential Revision:	https://reviews.freebsd.org/D8495
2016-11-17 07:33:37 +00:00