Commit Graph

17 Commits

Author SHA1 Message Date
jhb
00c3c01f4f Do a sweep of the tree replacing calls to pci_find_extcap() with calls to
pci_find_cap() instead.
2011-03-23 13:10:15 +00:00
jhb
2f51f05968 Fix some bugs in my last set of changes to ale(4):
- Remove extra unlock from end of ale_start_locked().
- Expand scope of locking in interrupt handler.
- Move ether_ifdetach() earlier and retire now-unneeded DETACH flag.

Tested by:	Aryeh Friedman
Reviewed by:	yongari (earlier version)
2011-01-18 16:27:40 +00:00
mdf
8045b08e4d sysctl(9) cleanup checkpoint: amd64 GENERIC builds cleanly.
Commit the rest of the devices.
2011-01-12 19:53:56 +00:00
jhb
be4690f32e Add a 'locked' variant of the foo_start() routine and call it directly
from interrupt handlers and watchdog routines instead of queueing a task
to call foo_start().

Reviewed by:	yongari
MFC after:	1 month
2011-01-03 18:28:30 +00:00
yongari
76e60b09a3 Remove unecessary and clearly wrong usage of atomic(9).
Reported by:  avg
2010-12-14 17:39:10 +00:00
marius
385153aa98 Convert the PHY drivers to honor the mii_flags passed down and convert
the NIC drivers as well as the PHY drivers to take advantage of the
mii_attach() introduced in r213878 to get rid of certain hacks. For
the most part these were:
- Artificially limiting miibus_{read,write}reg methods to certain PHY
  addresses; we now let mii_attach() only probe the PHY at the desired
  address(es) instead.
- PHY drivers setting MIIF_* flags based on the NIC driver they hang
  off from, partly even based on grabbing and using the softc of the
  parent; we now pass these flags down from the NIC to the PHY drivers
  via mii_attach(). This got us rid of all such hacks except those of
  brgphy() in combination with bce(4) and bge(4), which is way beyond
  what can be expressed with simple flags.

While at it, I took the opportunity to change the NIC drivers to pass
up the error returned by mii_attach() (previously by mii_phy_probe())
and unify the error message used in this case where and as appropriate
as mii_attach() actually can fail for a number of reasons, not just
because of no PHY(s) being present at the expected address(es).

Reviewed by:	jhb, yongari
2010-10-15 14:52:11 +00:00
yongari
92023f4cc9 Make sure to not use stale ip/tcp header pointers. The ip/tcp
header parser uses m_pullup(9) to get access to mbuf chain.
m_pullup(9) can allocate new mbuf chain and free old one if the
space left in the mbuf chain is not enough to hold requested
contiguous bytes. Previously drivers can use stale ip/tcp header
pointer if m_pullup(9) returned new mbuf chain.

Reported by:	Andrew Boyer (aboyer <> averesystems dot com)
MFC after:	10 days
2010-10-14 18:31:40 +00:00
yongari
bba9d9c06c It seems ale(4) controllers do not like to see TCP payload in the
first descriptor in TSO case. Otherwise controller can generate bad
frames during TSO. To address it, make sure to pull up ethernet +
IP + TCP header with options in first buffer. Also ensure the
buffer length of the first descriptor for TSO covers entire ethernet
+ IP + TCP with options and setup additional Tx descriptor if the
first buffer includes TCP payload.

Tested by:	Amar Takhar <verm <> darkbeer dot org >
MFC after:	1 week
2010-04-26 21:08:15 +00:00
yongari
66db61c8c0 With r206844, CSUM_TCP is also set for CSUM_TSO case. Modify
drivers to take into account for the change. Basically CSUM_TSO
should be checked before checking CSUM_TCP.
2010-04-19 22:10:40 +00:00
yongari
a519b2699d Add TSO support on VLANs. While I'm here remove unnecessary check
of VLAN hardware checksum offloading. vlan(4) already takes care of
this.
2010-02-26 22:46:36 +00:00
yongari
b9dd684580 Fix multicast handling. All Atheros controllers use big-endian form
in computing multicast hash.

PR:	kern/139137
2009-09-29 23:03:16 +00:00
yongari
f21ccb87b0 Disable Rx checksum offload until I find more clue why it breaks
under certain environments. However give users chance to override
it when he/she surely knows his/her hardware works with Rx checksum
offload.

Reported by:	Ulrich Spoerlein ( uqs <> spoerlein dot net )
MFC after:	1 week
Approved by:	re (kensmith)
2009-06-29 05:12:21 +00:00
rwatson
be5740a255 Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/
IF_ADDR_UNLOCK() across network device drivers when accessing the
per-interface multicast address list, if_multiaddrs.  This will
allow us to change the locking strategy without affecting our driver
programming interface or binary interface.

For two wireless drivers, remove unnecessary locking, since they
don't actually access the multicast address list.

Approved by:	re (kib)
MFC after:	6 weeks
2009-06-26 11:45:06 +00:00
yongari
c28665c9bf Now pci(4) handles PCIM_CMD_INTxDIS so there is no need to poke
this bit in driver.
2009-03-05 00:04:32 +00:00
yongari
d0222ccf63 AR8113 also need to set DMA read burst value. This should fix
occasional DMA read error seen on AR8113.

Submitted by:	Jie Yang < Jie.Yang <> Atheros com >
2008-12-03 09:01:12 +00:00
yongari
328878d459 Add some PHY magic to enable PHY hibernation and 1000baseT/10baseT
power adjustment. This change is required to guarantee correct
operation on certain switches.

Submitted by:	Jie Yang < Jie.Yang <> Atheros com >
2008-12-03 08:56:01 +00:00
yongari
8fe107d730 Add ale(4), a driver for Atheros AR8121/AR8113/AR8114 PCIe ethernet
controller. The controller is also known as L1E(AR8121) and
L2E(AR8113/AR8114). Unlike its predecessor Attansic L1,
AR8121/AR8113/AR8114 uses completely different Rx logic such that
it requires separate driver. Datasheet for AR81xx is not available
to open source driver writers but it shares large part of Tx and
PHY logic of L1. I still don't understand some part of register
meaning and some MAC statistics counters but the driver seems to
have no critical issues for performance and stability.

The AR81xx requires copy operation to pass received frames to upper
stack such that ale(4) consumes a lot of CPU cycles than that of
other controller. A couple of silicon bugs also adds more CPU
cycles to address the known hardware bug. However, if you have fast
CPU you can still saturate the link.
Currently ale(4) supports the following hardware features.
  - MSI.
  - TCP Segmentation offload.
  - Hardware VLAN tag insertion/stripping with checksum offload.
  - Tx TCP/UDP checksum offload and Rx IP/TCP/UDP checksum offload.
  - Tx/Rx interrupt moderation.
  - Hardware statistics counters.
  - Jumbo frame.
  - WOL.

AR81xx PCIe ethernet controllers are mainly found on ASUS EeePC or
P5Q series of ASUS motherboards. Special thanks to Jeremy Chadwick
who sent the hardware to me. Without his donation writing a driver
for AR81xx would never have been possible. Big thanks to all people
who reported feedback or tested patches.

HW donated by:	koitsu
Tested by:	bsam, Joao Barros <joao.barros <> gmail DOT com >
		Jan Henrik Sylvester <me <> janh DOT de >
		Ivan Brawley < ivan <> brawley DOT id DOT au >,
		CURRENT ML
2008-11-12 09:52:06 +00:00