handle address, where we're using handles as raw addresses.
This fixes devices with subregions on Octeon PCI specifically, and likely also on
MIPS more generally, where there isn't another bus_space in use that was doing the
math already.
long for specifying a boundary constraint.
- Change bus_dma tags to use bus_addr_t instead of bus_size_t for boundary
constraints.
These allow boundary constraints to be fully expressed for cases where
sizeof(bus_addr_t) != sizeof(bus_size_t). Specifically, it allows a
driver to properly specify a 4GB boundary in a PAE kernel.
Note that this cannot be safely MFC'd without a lot of compat shims due
to KBI changes, so I do not intend to merge it.
Reviewed by: scottl
- Reserver respective number of addresses for managment port
- octm uses base address directly
- other drivers get MACs on "first come first served" basis
Reviewed by: juli
- Centralize address assignment
- Make sure managment ports get first MAC address in pool
- Properly propagate fail if address allocation failed
Submitted by: Andrew Duane <aduane@juniper.net>
set all three of the kernel, supervisor, and user-mode 64-bit mode
flags. While FreeBSD does not currently use the supervisor ring (and
hence this is effectively a NOP on most systems), doing this avoids
triggering an exception on 64-bit MIPS CPUs that don't support 32-bit
compatibility mode, and therefore don't allow clearing the SX bit.
Reviewed by: gonzo
MFC after: 3 days
Sponsored by: DARPA, SRI International
Reading register $29 with RDHWR is becoming the de-facto standard to
implement TLS. According to linux-mips wiki, MIPS Technologies has
reserved hardware register $29 for ABI use. Furthermore current GCC
makes the following assumptions:
- RDHWR is natively available or otherwise emulated by the kernel
- Register $29 holds the TLS pointer
Submitted by: Robert Millan <rmh@debian.org>
of root HUB. Although it is initialized with port index of the
device's parent hub, which is worng. So track the USB tree up to
root HUB and initialize this filed ptroprly
Rename port_index to root_port_index in order to reflect its
real semantics.
on-board, glued to the AR71xx CPU. These may forgo separate WMAC EEPROMs
(which store configuration and calibration data) and instead store
it in the main board SPI flash.
Normally the NIC reads the EEPROM attached to it to setup various PCI
configuration registers. If this isn't done, the device will probe as
something different (eg 0x168c:abcd, or 0x168c:ff??.) Other setup registers
are also written to which may control important functions.
This introduces a new compile option, AR71XX_ATH_EEPROM, which enables the
use of this particular code. The ART offset in the SPI flash can be
specified as a hint against the relevant slot/device number, for example:
hint.pcib.0.bus.0.17.0.ath_fixup_addr=0x1fff1000
hint.pcib.0.bus.0.18.0.ath_fixup_addr=0x1fff5000
TODO:
* Think of a better name;
* Make the PCIe version of this fixup code also use this option;
* Maybe also check slot 19;
* This has to happen _before_ the SPI flash is set from memory-mapped
to SPI-IO - so document that somewhere.
- Use Elf32_Addr as default, the only field that is
64 bitw wide is R_MIPS_64
- Add R_MIPS_HIGHER and R_MIPS_HGHEST handlers
- Handle R_MIPS_HI16 and R_MIPS_LO16 for both .rel and
.rela sections
This was preventing the ath driver from being loaded at runtime.
It worked fine when compiled statically into the kernel but not when
kldload'ed after the system booted.
The root cause was that PCIR_INTLINE (register 60) was being
overwritten by zeros when register 62 was being written to.
A subsequent read of this register would return 0, and thus
the rest of the PCI glue assumed an IRQ resource had already
been allocated. This caused the device to fail to attach at
runtime as the device itself didn't contain any IRQ resources.
TODO: go back over the ar71xx and ar724x PCI config read/write
code and ensure it's correct.
comparing to struct timeval. for clocktime they should be
1..7 and 1..12 respectively
- CAPK-0100ND uses RTC without centruy bit (DS1307) so set it 21st
This is an AR71xx based board with 8MB flash, 64MB RAM, a
Mini-PCI+ slot (see below) and a single 10/100/1000baseT
ethernet port. It also has two USB ports.
This is an easier board than most to add as it doesn't have a
switch PHY on-board. This made it (mostly) trivial to craft a
working configuration.
Things to note:
* This, like most other reference boards, use uboot rather then
redboot. It means that you typically have to manually flash
both the kernel and rootfs partitions.
* Since there's currently no (nice) way to extract out the
ethernet MAC and RAM from the uboot environment, the RAM
will default to 32mb and the MAC will be something very
incorrect. I'll try to fix this up in a subsequent commit
or two, even if it's just some hard-coded nonsense in
ar71xx_machdep.c for now.
* The board is designed for a specific model of mini-PCI+
NIC which never made it into production. Normal mini-PCI
NICs will work fine; if you happen to have the NIC in question
then it will work fine with this board.
bits.
The ROUERSTATION and RSPRO variants contain:
* the board specific bits (eg the RTC for RSPRO, later on it'll
include the GPIO/LED definitions);
* the boot specific bits (eg, on-board flash, usb flash, etc).
For now the AR71XX_BASE file contains the common board config,
drivers and net80211/ath wireless drivers.
I'll follow this up with config files for the other boards I
have (eg the Ubiquiti LSSR71, as well as some Mikrotik boards
that use the AR71XX and atheros reference boards) which will
be quite easy to do now.
performance issues.
* Access to the GPIO bus is already locked by requesting
and releasing the bus - thus the lock isn't really needed
for each GPIO pin change.
* Don't lock and unlock the GPIO bus for -each- i2c access -
the i2c bus code is already doing this by calling the upper
layer callback to request/release the bus. This thus locks
the bus for the entirety of the transaction.
TODO:
* Further verify that everything is correctly requesting/
releasing the GPIO bus.
* Look at how to lock the GPIO pin configuration stuff,
potentially by locking/unlocking the bus at the gpiobus
layer.
At the moment grab and ungrab methods of all console drivers are no-ops.
Current intended meaning of the calls is that the kernel takes control of
console input. In the future the semantics may be extended to mean that
the calling thread takes full ownership of the console (e.g. console
output from other threads could be suspended).
Inspired by: bde
MFC after: 2 months
* Add in a default GPIO section for AR91XX_BASE.hints, which doesn't
define the GPIO function masks or any GPIO pines.
* Add in the GPIO line definitions for LEDs and GPIO pins for the
TP-WR1043nd.
I've verified the LEDs work fine using gpioset.
config and function mask setup.
* "gpiomask" now specifies which GPIO pins to enable, for devices to bind to.
* "function_set" allows bits in the function register to be set at GPIO setup.
* "function_clear" allows bits in the function register to be cleared at
GPIO setup.
The function_set/function_clear bits allow for individual GPIO pins to either
drive a GPIO line or an alternate function - eg USB, JTAG, etc. This allows
for things like CS1/CS2 be enabled for those boards w/ >1 SPI device connected,
or disabling JTAG for the AR7240 (which is apparently needed ..)
I've verified this on the AR71xx.
