Commit Graph

16 Commits

Author SHA1 Message Date
marius
4dc53a810b Recognize the SAB 82532 found in Fujitsu PRIMEPOWER650 and 900. 2011-05-15 13:27:38 +00:00
imp
49862b4836 Make iclear return int, since that matches all function definitions of it. 2009-02-05 19:32:34 +00:00
marcel
883428f9df With rev 1.24 of sys/powerpc/powermac/macio.c, we now get a
total of 6 interrupt resources for scc(4) on macio(4). This
is 3 per channel, of which the 1st of each channel is the
interrupt associated with the SCC. The other 2 are for DMA
operation.
Change scc_bfe_attach() to accept an argument that's the
number of interrupts per channel (ipc) and change each bus
front-end (bfe) to pass that argument through a wrapper
for the device_attach method.

For now, we only allocate the 1st interrupt of each channel
to perserve behaviour.
2008-04-26 18:40:59 +00:00
raj
ddcbd7a1c9 Support for Freescale QUad Integrated Communications Controller.
The QUICC engine is found on various Freescale parts including MPC85xx, and
provides multiple generic time-division serial channel resources, which are in
turn muxed/demuxed by the Serial Communications Controller (SCC).

Along with core QUICC/SCC functionality a uart(4)-compliant device driver is
provided which allows for serial ports over QUICC/SCC.

Approved by:	cognet (mentor)
Obtained from:	Juniper
MFp4:		e500
2008-03-03 18:20:17 +00:00
marcel
6a8f75121a Add method enabled() to the SCC interface. This method can be used
by driver backends to mark individual channels as enabled or not.
The default implementation of this method always mark channels as
enabled.
This method is currently not used, but is added with the PowerQUICC
in mind where the 2nd SCC channel can be disabled.
2007-03-28 18:05:17 +00:00
marcel
e5b7fa1b9f Allow the range of a SCC class to be 0. This gives all child
devices the same (overlapping) I/O range. This is useful for
embedded communications controllers like the CPM of various
models of the PowerQUICC.
2007-03-28 06:45:33 +00:00
marcel
9c3e35760f Pass the RID from the bus frontends to the core probe function.
Currently all RIDs are 0, but for PCI devices this typically
isn't the case. This change is made with future PCI support in
mind.
2007-03-22 23:45:25 +00:00
piso
6a2ffa86e5 o break newbus api: add a new argument of type driver_filter_t to
bus_setup_intr()

o add an int return code to all fast handlers

o retire INTR_FAST/IH_FAST

For more info: http://docs.freebsd.org/cgi/getmsg.cgi?fetch=465712+0+current/freebsd-current

Reviewed by: many
Approved by: re@
2007-02-23 12:19:07 +00:00
marcel
aedab5da36 Fix braino: The cl_range field should not hold the shifted I/O
space range per channel, but rather the unshifted range. The
shifting depends on the bus. The hardcoded shift was specific
to the SBus on sparc64. The shifted range is now determined at
run-time. This fixes the mac-io attachment.
2006-07-26 03:10:01 +00:00
marcel
5312caa99a Revert previous commit. Spinlocks hold interrupts disabled, so
preemption is not possible.

Pointed out by: jhb@
2006-07-25 00:23:54 +00:00
marcel
0473910011 If we have multiple interrupt resources, like for Z8530 clones on the
mac-io bus, we cannot setup FAST interrupt handlers. This because we
use spinlocks to protect the hardware and all interrupt resources are
assigned the same interrupt handler. When the interrupt handler is
invoked for interrupt X, it could be preempted for interrupt Y while
it was holding the lock (where X and Y are the interrupt resources
corresponding a single instance of this driver). This is a deadlock.
By only using a MPSAFE handler in that case we prevent preemption.
2006-07-24 22:25:16 +00:00
marcel
b5dd7f5b99 The Z8530 on the MacIO has an interrupt per channel. Deal with this
by having interrupt resource variables per channel. We don't set up
different interrupt handlers per channel, though.
2006-04-04 17:33:08 +00:00
marcel
cb5c5e62f7 Add a MacIO bus attachment. The Z8530 as present in the Mac needs
a different register shift and is fed by a different clock than
we use for UltraSPARC hardware. To deal with this, the regshft and
rclk fields in the class structure are removed and bus frontends
now pass the right regshft and rclk to the probe function where
they're put in the BAS and passed in to subordinate drivers.
2006-04-01 04:51:56 +00:00
marcel
ba3b8f1ee2 Fix cut-n-paste braino in previous commit: s/puc/scc/g
Pointy hat: marcel@
2006-03-31 21:55:53 +00:00
marcel
af78fcb5cc Add a DRIVER_MODULE declaration for fhc(4) as this attachement is
also used for the FHC bus.

Pointed out by: marius@
2006-03-31 17:39:49 +00:00
marcel
0215f8085c Add scc(4), a driver for serial communications controllers. These
controllers typically have multiple channels and support a number
of serial communications protocols. The scc(4) driver is itself
an umbrella driver that delegates the control over each channel
and mode to a subordinate driver (like uart(4)).
The scc(4) driver supports the Siemens SAB 82532 and the Zilog
Z8530 and replaces puc(4) for these devices.
2006-03-30 18:33:22 +00:00