Commit Graph

20 Commits

Author SHA1 Message Date
Pyun YongHyeon
96486faa6e Make sure to not use stale ip/tcp header pointers. The ip/tcp
header parser uses m_pullup(9) to get access to mbuf chain.
m_pullup(9) can allocate new mbuf chain and free old one if the
space left in the mbuf chain is not enough to hold requested
contiguous bytes. Previously drivers can use stale ip/tcp header
pointer if m_pullup(9) returned new mbuf chain.

Reported by:	Andrew Boyer (aboyer <> averesystems dot com)
MFC after:	10 days
2010-10-14 18:31:40 +00:00
Pyun YongHyeon
cb2f3e7f9b Backout r204230. TX mbuf parser for VLAN is still required to
enable TX checksum offloading if VLAN hardware tagging is disabled.
2010-10-14 17:57:52 +00:00
Xin LI
9ed03f0231 status bits should be &'ed against status to be really functional.
Reported by:	Jike Song
Reviewed by:	yongari
MFC after:	1 week
2010-09-16 21:06:23 +00:00
Pyun YongHyeon
5bec76e720 Make sure to disable RX MAC in alc_stop_mac(). Previously there
was a logic error which it always enabled RX MAC.
2010-08-13 19:39:33 +00:00
Pyun YongHyeon
2f70ccea9f Add support for Atheros AR8151/AR8152 PCIe gigabit/fast ethernet
controller. These controllers are known as L1D(AR8151) and
L2CB/B2(AR8152). This change adds supports for the following
controllers.
 o AR8151 v1.0(L1D) gigabit ethernet controller
 o AR8151 v2.0(L1D) gigabit ethernet controller
 o AR8152 v1.1(L2CB) fast ethernet controller
 o AR8152 v2.0(L2CB2) fast ethernet controller
These controllers have the same feature of AR8131/AR8132 and
support improved power saving control. The user visible change at
this moment is reduced jumbo frame size from 9KB to 6KB. Many
thanks to Atheros for continuing to support FreeBSD.

HW donated by:	Atheros Communications, Inc.
2010-08-09 17:28:08 +00:00
Pyun YongHyeon
a4d3574ccf Cache PCIY_PMG and PCIY_EXPRESS capability pointer to softc and use
it instead of calling pci_find_extcap().
2010-08-08 00:43:41 +00:00
Pyun YongHyeon
d62fc5de93 Remove unnecessary assignment. 2010-08-08 00:23:36 +00:00
Pyun YongHyeon
47ae892c85 Always disable ASPM L0s and enable L1 before entering into WOL
suspend state.  Also disable master clock after PHY power down,
this is supposed to save more power. The master clock should be
enabled if WOL is active.
2010-08-08 00:12:31 +00:00
Pyun YongHyeon
a0bca95502 Do not touch CMB TX threshold register when CMB is not used.
Note, alc(4) does not use CMB at all due to silicon bug.
2010-08-07 23:41:46 +00:00
Pyun YongHyeon
1e77baed0d Controller does not seem to support more than 1024 bytes DMA burst.
Limit DMA burst size to be less than or equal to 1024 bytes.
2010-08-07 23:33:06 +00:00
Pyun YongHyeon
7ee9ed98c6 Reduce Tx interrupt moderation timer from 50ms to 1ms. The default
value resulted in poor performance for UDP packets. With this
change, UDP bulk transfer performance is more than 940Mbps.

While I'm here fix a wrong register definition.
2010-08-06 00:50:16 +00:00
Pyun YongHyeon
6da6d0a9e3 With r206844, CSUM_TCP is also set for CSUM_TSO case. Modify
drivers to take into account for the change. Basically CSUM_TSO
should be checked before checking CSUM_TCP.
2010-04-19 22:10:40 +00:00
Pyun YongHyeon
01d60a6594 Remove Tx mbuf parsing code for VLAN in TSO path. Controller does
not support TSO over VLAN if VLAN hardware tagging is disabled so
there is no need to check VLAN here.
2010-02-22 23:35:35 +00:00
Pyun YongHyeon
e67344a3be Add TSO support on VLANs. Also make sure to update TSO capability
whenever jumbo frame is configured.
While I'm here remove unnecessary check of VLAN hardware checksum
offloading. vlan(4) already takes care of this.
2010-02-22 22:41:27 +00:00
Pyun YongHyeon
cb2cdeceb5 Fix multicast handling. All Atheros controllers use big-endian form
in computing multicast hash.

PR:	kern/139137
2009-09-29 23:03:16 +00:00
Pyun YongHyeon
e34135013b For AR8132 fast ethernet controller, do not report 1000baseT
capability to mii(4). Even though AR8132 uses the same model/
revision number of F1 gigabit PHY, the PHY has no ability to
establish 1000baseT link. I have no idea why Atheros use the same
device/model id for this PHY.
With this change atphy(4) does not report 1000baseT media
capability and manual 1000baseT configuration is also disabled
which is more desirable behavior for 10/100Mbps PHY.
2009-09-28 22:18:38 +00:00
Pyun YongHyeon
e4d5e24821 Don't try to power down PHY when alc(4) failed to map the device.
This fixes system crash when mapping alc(4) device failed in device
attach.

Reported by:	Jim < stapleton.41 <> gmail DOT com >
MFC after:	3 days
2009-08-24 20:37:15 +00:00
Kevin Lo
6ece67d83f Free allocated Rx ring dma memory/tags.
Reviewed by: yongari@
Approved by: re (kib)
2009-07-31 09:57:42 +00:00
Robert Watson
eb956cd041 Use if_maddr_rlock()/if_maddr_runlock() rather than IF_ADDR_LOCK()/
IF_ADDR_UNLOCK() across network device drivers when accessing the
per-interface multicast address list, if_multiaddrs.  This will
allow us to change the locking strategy without affecting our driver
programming interface or binary interface.

For two wireless drivers, remove unnecessary locking, since they
don't actually access the multicast address list.

Approved by:	re (kib)
MFC after:	6 weeks
2009-06-26 11:45:06 +00:00
Pyun YongHyeon
d68875eb7e Add alc(4), a driver for Atheros AR8131/AR8132 PCIe ethernet
controller. These controllers are also known as L1C(AR8131) and
L2C(AR8132) respectively. These controllers resembles the first
generation controller L1 but usage of different descriptor format
and new register mappings over L1 register space requires a new
driver. There are a couple of registers I still don't understand
but the driver seems to have no critical issues for performance and
stability. Currently alc(4) supports the following hardware
features.
  o MSI
  o TCP Segmentation offload
  o Hardware VLAN tag insertion/stripping
  o Tx/Rx interrupt moderation
  o Hardware statistics counters(dev.alc.%d.stats)
  o Jumbo frame
  o WOL
AR8131/AR8132 also supports Tx checksum offloading but I disabled
it due to stability issues. I'm not sure this comes from broken
sample boards or hardware bugs. If you know your controller works
without problems you can still enable it. The controller has a
silicon bug for Rx checksum offloading, so the feature was not
implemented.
I'd like to say big thanks to Atheros. Atheros kindly sent sample
boards to me and answered several questions I had.

HW donated by:	Atheros Communications, Inc.
2009-06-10 02:07:58 +00:00