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9 Commits

Author SHA1 Message Date
rrs
8bf38c1934 Update the hwpmc driver to have the new type HASWELL_XEON. Also 
go back through HASWELL, IVY_BRIDGE, IVY_BRIDGE_XEON and SANDY_BRIDGE
to straighten out all the missing PMCs. We also add a new pmc tool
pmcstudy, this allows one to run the various formulas from
the documents "Using Intel Vtune Amplifier XE on XXX Generation platforms" for
IB/SB and Haswell. The tool also allows one to postulate your own
formulas with any of the various PMC's. At some point I will enahance
this to work with Brendan Gregg's flame-graphs so we can flamegraph
various PMC interactions. Note the manual page also needs some
work (lots of work) but gnn has committed to help me with that ;-)
Reviewed by: gnn
MFC after:1 month
Sponsored by:	Netflix Inc.
 2015-01-14 12:46:58 +00:00
eadler
1130a4041b Fix pointer type in call to malloc 
Submitted by:	Meyer, Conrad conrad.meyer@isilon.com
 2014-03-13 16:51:40 +00:00
jhb
b2533ec507 Move <machine/apicvar.h> to <x86/apicvar.h>. 2014-01-23 20:10:22 +00:00
sbruno
20a2c3e096 Trailing whitespace cleanup along with 80 column enforcemnt. 
Submitted by:	hiren.panchasara@gmail.com
Reviewed by:	sbruno@freebsd.org
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
 2013-04-03 21:34:35 +00:00
sbruno
18d941830f Update hwpmc to support Haswell class processors. 
0x3C:      /* Per Intel document 325462-045US 01/2013. */

Add manpage to document all the goodness that is available in this
processor model.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris, sbruno
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
 2013-03-28 19:15:54 +00:00
davide
8636a37ecc - Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) 
- New manpages with event lists.
- Add MSRs for the Intel Sandy Bridge microarchitecture

Reviewed by:	attilio, brueffer, fabient
Approved by:	gnn (mentor)
MFC after:	3 weeks
 2012-03-01 21:23:26 +00:00
gnn
405e6f5ec5 Clean up a switch statement for uncore events on Westmere processors. 
Submitted by:	Davide Italiano
Reviewed by:	gnn
MFC after:	1 week
 2012-01-13 17:13:46 +00:00
fabient
ca76b8cdad Add missing MSR programming for some events. 
Submitted by:	Davide Italiano <davide.italiano@gmail.com>
MFC after:	3 days
 2012-01-04 07:33:06 +00:00
fabient
85d5b2855f - Support for uncore counting events: one fixed PMC with the uncore 
domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
  There is some removed events in the documentation, they have been
  kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.

Sponsored by: NETASQ
 2010-04-02 13:23:49 +00:00