Commit Graph

73 Commits

Author SHA1 Message Date
mav
863be0d261 Do not force AHCI mode on NVIDIA MCP89 SATA controllers. Recent Apple
Mac with this chipset does not initialize AHCI mode unless it is started
from EFI loader.  However, legacy ATA mode works.

Submitted by:	jkim@ (original version)
Approved by:	re (kib)
MFC after:	1 week
2011-08-02 11:07:47 +00:00
mav
b55bc3f9ac In some cases, at least on Marvell 88SE912x controllers, Current Command
Slot field of the PxCMD register may point to an empty command slot.
That breaks command timeout detection logic, making impossible to find
what command actually caused timeout, and leading to infinite wait.
Workaround that by checking whether pointed command slot is really used
and can timeout in its time. And if not, fallback to the dumb algorithm
used with FBS -- let all commands to time out and then fail all of them.

Approved by:	re (kib)
MFC after:	1 week
2011-07-29 20:35:23 +00:00
mav
e3da28b046 Add ID for Marvell 88SE9125 SATA controller.
PR:		kern/157843
MFC after:	1 week
2011-06-30 19:23:17 +00:00
mav
8e3cfdbdaa Add Marvell 88SE9172 chip PCI ID. 2011-05-26 10:10:10 +00:00
mav
7169c920dd Marvell 88SE91xx controllers are known to report soft-reset completion
without waiting for device readiness (or at least not updating FIS receive
area in time). To workaround that, special quirk was added earlier to wait
for the FIS receive area update. But it was found that under same PCI ID
0x91231b4b and revision 0x11 there are two completely different chip
versions (firmware?): HBA and RAID. The problem is that RAID version in
some cases, such as hot-plug, does not update FIS receive area at all!

To workaround that, differentiate the chip versions by their capabilities,
and, if RAID version found, skip FIS receive area update waiting and read
device signature from the PxSIG register instead. This method doesn't work
for HBA version when PMP attached, so keep using previous workaround there.
2011-05-26 09:23:01 +00:00
mav
ddcb287699 According to SATA specification, when Serial ATA Enclosure Management Bridge
(SEMB) is unable to communicate to Storage Enclosure Processor (SEP), in
response to hard and soft resets it should among other things return value
0x7F in Status register. The weird side is that it means DRQ bit set, which
tells that reset request is not completed. It would be fine if SEMB was the
only device on port. But if SEMB connected to PMP or built into it, it may
block access to other devices sharing same SATA port.

Make some tunings/fixes to soft-reset handling to workaround the issue:
 - ahci(4): request CLO on the port after soft reset to ignore DRQ bit;
 - siis(4): gracefully reinitialize port after soft reset timeout (hardware
doesn't detect reset request completion in this case);
 - mvs(4): if PMP is used, send dummy soft-reset to the PMP port to make it
clear DRQ bit for us.

For now this makes quirks in ata_pmp.c, hiding SEMB ports of SiI3726/SiI4726
PMPs, less important. Further, if hardware permit, I hope to implement real
SEMB support.
2011-05-25 13:55:49 +00:00
mav
d7d39d0277 Add support for "LED" enclosure management messages, defined by the AHCI.
When supported by hardware, this allows to control per-port activity, locate
and fault LEDs via the led(4) API for localization and status reporting
purposes. Supporting AHCI controllers may transmit that information to the
backplane controllers via SGPIO interface. Backplane controllers interpret
received statuses in some way (IBPI standard) to report them using present
indicators.
2011-05-17 22:07:45 +00:00
jfv
3cb21d8ed2 Chipset support for the new Intel Panther Point PCH, thanks
to Seth Heasley for preparing the changes.
2011-05-11 20:31:27 +00:00
mav
e808412d86 Add PCI ID for Marvell 88SE9182 -- PCIe 2.x x2 relative of the 88SE912x.
Submitted by:	dchagin
MFC after:	1 week
2011-05-05 17:11:26 +00:00
mav
ccce60bdeb Fix some English grammar. 2011-04-19 10:57:40 +00:00
mav
0b4c448250 According to specification. device should respond to COMRESET with COMINIT
in no more then 10ms. If we detected no device presence within that time,
there is no reason to wait longer.
2011-04-19 10:51:19 +00:00
mav
cc8f016bc1 Properly handle memory allocation errors during error recovery. 2011-04-19 08:01:17 +00:00
mav
af7a233f61 Handle ready timeout during polled operation same as done in mvs(4) before. 2011-04-18 16:00:46 +00:00
mav
ced1036047 - Tune different wait loops to cut some more milliseconds from reset time.
- Do not call ahci_start() before device signature received. It is required
by the specification and caused non-fatal reset timeouts on AMD chipsets.
2011-04-18 13:34:31 +00:00
mav
2a9c0a02ca Some changes around hot-plug and interface power-management:
- use ATA_SE_EXCHANGED (SError.DIAG.X) bit to detect hot-plug events when
power-management enabled and ATA_SE_PHY_CHANGED (SError.DIAG.N) can't be
trusted;
 - on controllers supporting staggered spin-up (SS) put unused channels
into Listen state instead of Off. It should still save some power, but
allow plug-in events to be detected;
 - on controllers supporting cold presence detection (CPD), when power
management enabled, use CPD events to detect hot-plug in addition to PHY
events.
2011-04-15 16:40:31 +00:00
mav
193a7ed98c Improve SATA Asynchronous Notification feature support in CAM:
- make SATA SIMs announce capabilities to handle SDB with Notification bit;
 - make PMP driver honor this SIMs capability;
 - make SATA XPT to negotiate and enable this feature for ATAPI devices.

This feature allows supporting SATA ATAPI devices to inform system about
some events happened, that may require attention. In my case this allows
LG GH22LS50 SATA DVR-RW drive to report tray open/close events. Events
reported to CAM in form of AC_SCSI_AEN async. Further they could be used
as a hints for checking device status and reporting media change to upper
layers, for example, via spoiling mechanism of GEOM.
2011-04-13 16:20:54 +00:00
mav
93b6f3ee5d Refactor hard-reset implementation in ahci(4).
Instead of spinning in a tight loop for up to 15 seconds, polling for device
readiness while it spins up, return reset completion just after PHY reports
"connect well" or 100ms connection timeout. If device was found, use callout
for checking device readiness with 100ms period up to full 31 second timeout.

This fixes system freeze for 5-10 seconds on drives hot plug-in.
2011-04-12 20:50:57 +00:00
mav
983e9f3338 Implement automatic SCSI sense fetching for ahci(4). 2011-04-12 11:24:59 +00:00
mav
8c9d6ff80b Add one more ID for Marvell 88SE912x chip found on Asus U3S6 card.
Submitted by:	Jonas Jonsson <fatbrain@gmail.com>
2011-04-07 08:28:53 +00:00
mav
2868a01f09 Add some more IDs of HighPoint RocketRAID 64x. 2011-03-06 16:10:39 +00:00
mav
4df7e87e2c Restore DH89xxCC/Patsburg chip IDs accentally dropped at r218596. 2011-02-12 13:28:50 +00:00
mav
419b2b4687 Disable NCQ for multiport Marvell 88SX61XX SATA controllers. Simultaneous
active I/O to several disks (copying large file on ZFS) causes timeout after
just a few seconds of run. Single port 88SX6111 seems like not affected.

Skip reading transferred bytes count for these controllers. It works for
88SX6111, but 88SX6145 always returns zero there. Haven't tested others,
but better to be safe.
2011-02-12 07:06:40 +00:00
jfv
c4f814b2fb Support for the new Patsburg PCH chipset:
- SMBus Controller
     - SATA Controller
     - HD Audio Controller
     - Watchdog Controller

Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code.

MFC after 3 days
2011-02-01 01:05:11 +00:00
jfv
ec8c08c081 Support for the new DH89xxCC PCH chipset including:
- SATA controller
      - Watchdog timer
      - SMBus controller
2011-01-31 18:41:52 +00:00
mav
769825141b Add IDs for HighPoint RocketRAID 64x controllers.
These controllers consist of two Marvell 88SE9128 6Gbps SATA chips and
PLX PCIe bridge. As result, they seem to be agree to work with ahci(4)
as usual HBAs. The only noticed issue is that RAID BIOS disables all
drive caches during boot, though `camcontrol cmd ...` is able to fix that.

Those who wants RAID functionality can still use closed proprietary driver
from HighPoint site.

MFC after:	1 week
2011-01-10 22:27:52 +00:00
mav
6c063f9e37 Add IDs of HighPoint RocketRAID 62x cards (Marvell 88SE9128 chips).
PR:		kern/152926
Submitted by:	Mike Tancsa <mike@sentex.net>
MFC after:	1 week
2010-12-08 20:35:20 +00:00
mav
36ae5df8ce Fix small typo.
Submitted by:	Artem Belevich
2010-11-22 23:04:25 +00:00
mav
78df14851a Teach ahci(4), siis(4) and ATA_CAM ata(4) wrapper report to CAM residual
I/O length on underruns, that often happens for some SCSI commands.
2010-11-08 15:36:15 +00:00
mav
00e9a82e78 Add missing mtx_destroy() on channel attach failure. 2010-10-25 07:41:21 +00:00
mav
c24aa138ad Fix panic, when due to some kind of congestion on FIS-based switching
port multiplier some command triggers false positive timeout, but then
completes normally.

MFC after:	2 weeks
2010-09-16 12:39:50 +00:00
mav
0c82a20a06 MFata(4):
Add Intel Cougar Point PCH SATA Controller DeviceIDs. Correct some existing
entries for Intel Ibex Peak (5 Series/3400 Series) PCH SATA controllers.
2010-08-28 07:24:45 +00:00
mav
68b26f6649 Export PCI IDs of ATA/SATA controllers through CAM and ata(4) layers to
GEOM. This information needed for proper soft-RAID's on-disk metadata
reading and writing.
2010-07-25 15:43:52 +00:00
mav
e4e19d26b0 Disable NCQ and PMP support for VIA VT8251 AHCI. It was reported to be
unreliable under load. Linux does the same.
2010-06-08 10:03:08 +00:00
mav
265a7f94f2 Plug memory leak to silent Coverity. Error is still not really handled.
Found with:   Coverity Prevent(tm)
CID:          4130
2010-06-05 08:07:54 +00:00
mav
d49dd00196 Fix attach errors handling.
Found with:   Coverity Prevent(tm)
CID:          3424
2010-06-05 08:02:19 +00:00
mav
98a829859d Fill rman range start/end values. It makes devinfo output more readable. 2010-05-22 08:30:47 +00:00
mav
810a32455d Report ATA/SATA channel number to NewBus at location string. 2010-05-22 07:32:47 +00:00
mav
e4bb679c99 Improve suspend/resume support. Make sure controller is idle on suspend
and reset it on resume.
2010-05-21 13:29:28 +00:00
mav
0291fae914 Enable PCI busmastering explicitly to be sure. 2010-05-02 14:46:05 +00:00
mav
90843ddc5c Make SATA XPT negotiate and enable some additional SATA features, such as:
- device initiated power management (some devices support only this way);
 - Automatic Partial to Slumber Transition (more power saving);
 - DMA auto-activation (expected to slightly improve performance).
More features could be added later, when hardware supports.
2010-05-02 12:07:47 +00:00
mav
295ded74b5 Add Target/LUN ID checks and deny access to targets 1-14 when PMP absent.
Enforce PMA bit clearing when PMP detached to avoid further scan timeouts.
2010-04-30 08:02:12 +00:00
rpaulo
a30dd37469 Revert r206755. It causes some laptops to stop booting. 2010-04-19 14:07:33 +00:00
rpaulo
afee887128 Add another ICH7M chipset that works.
MFC after:	1 week
2010-04-17 11:40:39 +00:00
mav
ef7941cba2 - Spec tells that CCC interrupt is edge triggered. Acknowledge it as such.
- Do not try to enable CCC if it is not supported.
2010-03-21 18:18:58 +00:00
mav
e42f354e73 MFp4:
With FBS enabled, we have no idea what command caused timeout.
Implement same logic as in siis(4) - wait for other commands
complete or timeout and then give some more time.
2010-02-14 12:30:35 +00:00
mav
ae13510651 Disable PHY of unconnected ports when interface power management enabled.
It allows to save a bit more power (about 0.5W on 2 unused ports of ICH8M).
2010-02-03 12:00:57 +00:00
mav
b5b6d6b0e0 - Give ATA/SATA SIMs info about ATAPI packet size, supported by device.
- Make ATA XPT to reject longer SCSI CDBs then supported by device, or
any SCSI CDBs, if device doesn't support ATAPI.
2010-02-02 11:09:28 +00:00
mav
d4a8a5b0f9 Reset port on disconnect event, to abort any running requests. 2010-01-29 12:47:04 +00:00
mav
39c73ee5aa Add FIS-based switching support. If controller supports FBS, it allows
several devices beyond Port Multiplier to work simultaneously, substantially
increasing performance.
2010-01-28 17:54:47 +00:00
mav
72062fdcec MFp4: Large set of CAM inprovements.
- Unify bus reset/probe sequence. Whenever bus attached at boot or later,
CAM will automatically reset and scan it. It allows to remove duplicate
code from many drivers.
- Any bus, attached before CAM completed it's boot-time initialization,
will equally join to the process, delaying boot if needed.
- New kern.cam.boot_delay loader tunable should help controllers that
are still unable to register their buses in time (such as slow USB/
PCCard/ CardBus devices), by adding one more event to wait on boot.
- To allow synchronization between different CAM levels, concept of
requests priorities was extended. Priorities now split between several
"run levels". Device can be freezed at specified level, allowing higher
priority requests to pass. For example, no payload requests allowed,
until PMP driver enable port. ATA XPT negotiate transfer parameters,
periph driver configure caching and so on.
- Frozen requests are no more counted by request allocation scheduler.
It fixes deadlocks, when frozen low priority payload requests occupying
slots, required by higher levels to manage theit execution.
- Two last changes were holding proper ATA reinitialization and error
recovery implementation. Now it is done: SATA controllers and Port
Multipliers now implement automatic hot-plug and should correctly
recover from timeouts and bus resets.
- Improve SCSI error recovery for devices on buses without automatic sense
reporting, such as ATAPI or USB. For example, it allows CAM to wait, while
CD drive loads disk, instead of immediately return error status.
- Decapitalize diagnostic messages and make them more readable and sensible.
- Teach PMP driver to limit maximum speed on fan-out ports.
- Make boot wait for PMP scan completes, and make rescan more reliable.
- Fix pass driver, to return CCB to user level in case of error.
- Increase number of retries in cd driver, as device may return several UAs.
2010-01-28 08:41:30 +00:00