Commit Graph

52 Commits

Author SHA1 Message Date
Warner Losh
8cb2906936 Add a define for the Standard SD Host Controller Base Peripheral. 2006-05-30 21:36:12 +00:00
Warner Losh
8d10dd1a82 Make RID2BAR actually return a number that can be plugged into PCIR_BAR()
rather than a bitmask.

Submitted by: ru@
2005-12-30 20:25:40 +00:00
Warner Losh
b60c6f4683 Add a macro to map from BAR to rid # (inverse of PCIR_BARS). 2005-12-29 23:40:41 +00:00
John Baldwin
4f9795b9fe Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used
to search for a specific extended capability.  If the specified capability
is found for the given device, then the function returns success and
optionally returns the offset of that capability.  If the capability is
not found, the function returns an error.
2005-12-20 19:57:47 +00:00
Warner Losh
87623e8dd6 Use symbolic name rather thanhard coding the cap pointer offset for
type two devices.
2005-10-29 05:49:06 +00:00
Warner Losh
00b02fa185 Add PCIM_BIOS_ADDR_MASK too 2005-10-28 06:02:51 +00:00
Warner Losh
0ec342c524 Some cardbus CIS definitions moved here since they are PCI registers. 2005-10-28 05:57:10 +00:00
Warner Losh
f8749e3d9b As threatened by BURN_BRIDGES, restire PCIR_MAPS and PCIR_HEADERTYPE 2005-06-05 23:08:59 +00:00
Marcel Moolenaar
d1ee178775 Add defines for the Bridge Control Register bits.
Obtained from: jhb@
2005-04-29 01:58:27 +00:00
John-Mark Gurney
0e49742d03 fix misspelling of 0x30...
Spotted by:	reviewing MFC commit
2005-04-01 22:56:37 +00:00
John-Mark Gurney
1a82818b98 fix a copy/paste typo for scanner/gameport...
Spotted by:	Michal Mertl <mime@traveller.cz>
2005-03-26 22:17:48 +00:00
John-Mark Gurney
4ea3b0e7e2 add some additional pci classes and sub-classes..
Reviewed by:	imp (almost 6 months ago)
2005-03-26 20:31:09 +00:00
Warner Losh
098ca2bda9 Start each of the license/copyright comments with /*-, minor shuffle of lines 2005-01-06 01:43:34 +00:00
Scott Long
ec40a9f9d0 Teach the PCI code to parse MSI extended capabilities. Re-arrange the
pcicfg struct a bit to hold extcap structures instead of structure members.
2003-09-14 19:30:00 +00:00
Scott Long
3c358d0ca0 Expand the extended capabilities list and add definitions for MSI. 2003-09-14 14:42:26 +00:00
John Baldwin
b66752c4a1 Bring back PCIR_HEADERTYPE as an alias for PCIR_HDRTYPE under BURN_BRIDGES
for backwards compat.  The old name will be gone in 6.0, but will be
around in 5.x.  This will help unbreak 3rd party code, e.g. the nvidia
DRM module.
2003-09-03 17:48:22 +00:00
John Baldwin
56802c46e2 - Deprecate PCIR_MAPS under BURN_BRIDGES (meaning it will be gone in 6.0)
and replace it with the more intuitive name PCIR_BARS.
- Add a PCIR_BAR(x) macro that returns the config space register offset of
  the 32-bit BAR x.

MFC after:	3 days
2003-09-02 17:11:27 +00:00
John Baldwin
729d7ffbcf - Rename PCIx_HEADERTYPE* to PCIx_HDRTYPE* so the constants aren't so long.
- Add a new PCIM_HDRTYPE constant for the field in PCIR_HDRTYPE that holds
  the header type.
- Replace several magic numbers with appropriate constants for the header
  type register and a couple of PCI_FUNCMAX.
- Merge to amd64 the fix to the i386 bridge code to skip devices with
  unknown header types.

Requested by:	imp (1, 2)
2003-08-28 21:22:25 +00:00
John Baldwin
86889ca086 Add constants for capability IDs and header types.
Submitted by:	Samy Al Bahra <samy@kerneled.com>
2003-08-28 20:59:31 +00:00
Warner Losh
8d50cc0e3e Define PCI_MAXHDRTYPE to be 2. We know about header types 0, 1 and 2.
Update the MI device scanning code to use PCI_MAXHDRTYPE rather than
the hard coded 2.
2003-08-01 21:45:56 +00:00
Dag-Erling Smørgrav
bd9155712b Add constants for USB programming interfaces. These are already defined
(with other names) in the USB driver sources, but I felt that pcireg.h
should have a complete list - at least of classes and interfaces that we
know about and use.
2003-04-23 15:51:36 +00:00
Justin T. Gibbs
eda578ae9f Add some PCI-X register definitions.
PCIM_CMD_SERREN -> PCIM_CMD_SERRESPEN to be consistent with
the PERR definition.
2002-06-05 22:25:51 +00:00
Justin T. Gibbs
98f89aa0a9 Add PCIR_CAP_PTR as a define for the location of the capability
pointer of type 0 devices.  This is required by my last aic7xxx change.
2000-12-20 14:36:52 +00:00
Mike Smith
8983cfbf27 Next round of PCI subsystem updates:
- Break out the /dev/pci driver into a separate file.
 - Kill the COMPAT_OLDPCI support.
 - Make the EISA bridge attach a bit more like the old code; explicitly
   check for the existence of eisa0/isa0 and only attach if they don't
   already exist.  Only make one bus_generic_attach() pass over the
   bridge, once both busses are attached.  Note that the stupid Intel
   bridge's class is entirely unpredictable.
 - Add prototypes and re-layout the core PCI modules in line with
   current coding standards (not a major whitespace change, just moving
   the module data to the top of the file).
 - Remove redundant type-2 bridge support from the core PCI code; the
   PCI-CardBus code does this itself internally.  Remove the now
   entirely redundant header-class-specific support, as well as the
   secondary and subordinate bus number fields.  These are bridge
   attributes now.
 - Add support for PCI Extended Capabilities.
 - Add support for PCI Power Management.  The interface currently
   allows a driver to query and set the power state of a device.
 - Add helper functions to allow drivers to enable/disable busmastering
   and the decoding of I/O and memory ranges.
 - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some
   places.
 - Make the PCI-PCI bridge code a little more paranoid about valid
   I/O and memory decodes.
 - Add some more PCI register definitions for the command and status
   registers.  Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
Mike Smith
4fa59183f1 - We have access to our own device_t here, so use pci_read_config
rather than finding our parent pcib and using its PCI_READ_CONFIG
   method.

 - Fix the defines for the 32-bit I/O decode registers, and properly
   process the 16-bit versions.  Now we will correctly check that I/O
   resources behind the bridge are going to be decoded.

 - Bring the quirk for the Orion PCI:PCI bridge in here (since it
   seems to want to set the secondary/supplementary bus numbers).

 - Use PCI_SLOTMAX rather than a magic number.
2000-12-12 13:20:35 +00:00
Archie Cobbs
645d61ffeb Add definition for PCIS_SERIALBUS_SMBUS PCI device subclass.
Remove cut & paste leftovers.
2000-10-02 00:41:43 +00:00
Justin T. Gibbs
cb4d93cdbf Add PCIM_CMD_MWRICEN, the bit in the command register in PCI space
that enables memory write and invalidate cycles on a bus master.
2000-09-16 20:06:13 +00:00
Peter Wemm
30d1c11e3a Encapsulate the old PCI compatability support and APIs completely under
"options COMPAT_OLDPCI".  This option already existed, but now also tidies
up the declarations in #include <pci/pci*.h>.  It is amazing how much stuff
was using the old pre-FreeBSD 3.x names and going silently undetected.
2000-05-28 16:35:57 +00:00
Kazutaka YOKOTA
689e7081eb Added PCIR_BIOS (0x30). 2000-01-10 12:53:19 +00:00
Peter Wemm
649f6f6393 Add the 16550 programming interface code for PCIS_SIMPLECOMM_UART. 1999-10-09 16:00:56 +00:00
Peter Wemm
c3aac50f28 $Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00
Peter Wemm
6182fdbda8 Bring the 'new-bus' to the i386. This extensively changes the way the
i386 platform boots, it is no longer ISA-centric, and is fully dynamic.
Most old drivers compile and run without modification via 'compatability
shims' to enable a smoother transition.  eisa, isapnp and pccard* are
not yet using the new resource manager.  Once fully converted, all drivers
will be loadable, including PCI and ISA.

(Some other changes appear to have snuck in, including a port of Soren's
 ATA driver to the Alpha.  Soren, back this out if you need to.)

This is a checkpoint of work-in-progress, but is quite functional.

The bulk of the work was done over the last few years by Doug Rabson and
Garrett Wollman.

Approved by:	core
1999-04-16 21:22:55 +00:00
Justin T. Gibbs
6405ed07d7 ahc_pci.c:
Disable DPARCKEN in the DSCOMMAND0 register on the aic7890/91/96/97.
	Parity checking is broken for some chip/MB combinations and this
	is the work around recommended by Adaptec.

dpt_pci.c:
	Remove a superflous '{' that prevented DPT_ALLOW_MEMIO from working.

pcireg.h:
	Add a definition for Parity Error Reponse bit in the PCI Space
	command register.
1998-10-07 03:40:51 +00:00
John Dyson
e871e61fcf Addition of support of the slightly rogue Promise IDE interface(Dyson), support
of multiple PCI IDE controllers(Dyson), and some updates and cleanups from
John Hood, who originally made our IDE DMA stuff work :-).

I have run tests with 7 IDE drives connected to my system, all in DMA
mode, with no errors.  Modulo any bugs, this stuff makes IDE look
really good (within it's limitations.)

Submitted by:	John Hood <cgull@smoke.marlboro.vt.us>
1997-09-20 07:41:58 +00:00
Peter Wemm
2ac7b161fb PCI_CLASS_MASS_STORAGE (under PCI_COMPAT) was used in a driver in LINT
still (stallion.c).
1997-06-01 16:00:43 +00:00
Stefan Eßer
b9d14bed1d Add one more compatibility define to make the Adaptec driver compile
with option AHC_ALLOW_MEMIO again ....
1997-05-28 20:37:19 +00:00
Stefan Eßer
903f376ec8 Define command register enable bits, which are required for a consitency
test added to pci_compat.c
1997-05-28 11:15:18 +00:00
Stefan Eßer
5bec615793 Completely replace the PCI bus driver code to make it better reflect
reality. There will be a new call interface, but for now the file
pci_compat.c (which is to be deleted, after all drivers are converted)
provides an emulation of the old PCI bus driver functions. The only
change that might be visible to drivers is, that the type pcici_t
(which had been meant to be just a handle, whose exact definition
should not be relied on), has been converted into a pcicfgregs* .

The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t
and has been converted to just call the PCI drivers functions to access
configuration space register, instead of inventing its own ...

This code is by no means complete, but assumed to be fully operational,
and brings the official code base more in line with my development code.

A new generic device descriptor data type has to be agreed on. The PCI
code will then use that data type to provide new functionality:

1) userconfig support
2) "wired" PCI devices
3) conflicts checking against ISA/EISA
4) maps will depend on the command register enable bits
5) PCI to Anything bridges can be defined as devices,
   and are probed like any "standard" PCI device.

The following features are currently missing, but will be added back,
soon:

1) unknown device probe message
2) suppression of "mirrored" devices caused by ancient, broken chip-sets

This code relies on generic shared interrupt support just commited to
kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
Stefan Eßer
760b5bf213 Add definition of PCI_SUBID_REG2, the subvendor/device ID for
a header type 2 device.
1997-04-24 08:03:31 +00:00
Poul-Henning Kamp
e4ccad941f The bit of the cardbus bridge support code se and I have been able to agree
on so far... :-)
Reviewed by:	se
1997-04-20 06:57:43 +00:00
Peter Wemm
6875d25465 Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not
ready for it yet.
1997-02-22 09:48:43 +00:00
Jordan K. Hubbard
1130b656e5 Make the long-awaited change from $Id$ to $FreeBSD$
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.

Boy, I'm glad we're not using sup anymore.  This update would have been
insane otherwise.
1997-01-14 07:20:47 +00:00
Stefan Eßer
576b74fcc8 Add support for header type == 1 devices (PCI 2.1 compatible PCI to PCI
bridges with support for 64 bit memory addresses and 32 bit I/O addresses).

The code is not complete. It ignores the upper half of the long addresses.
This is not a problem on PC compatible systems, but has to be fixed for
real computers.
1996-11-12 23:18:12 +00:00
Stefan Eßer
c88529d0e9 Fix PCI to PCI bridge register bit field masks.
Thanks to "Mike Durian" <durian@plutotech.com> for the very good
problem report and his support as a beta tester of this patch.
1996-11-12 23:10:24 +00:00
Stefan Eßer
10e966fae4 Add support for ioctl() accesses to PCI config space registers.
Garrett Wollman sent me this code a few weeks ago for review, and I made
some significant changes, which he in turn accepted ...

In order to make use of these changes, a device entry has to added to /dev.

Submitted by:	wollman
1996-10-22 20:20:14 +00:00
Stefan Eßer
e653d76e96 Add support for multi-function devices. 1996-01-25 18:32:00 +00:00
Stefan Eßer
b23345605d Fix bad typo: > was used instead of >> ...
Submitted by:	Matt Thomas <matt@lkg.dec.com>
1996-01-19 19:03:47 +00:00
Stefan Eßer
8673e05a9a Completely new PCI code:
1) Supports PCI to PCI bridge devices (and tries to initialise them,
   even if the BIOS is brain dead).
2) Supports shared PCI interrupts. Interrupt handlers now MUST return
   '0' if they found nothing to do, '1' otherwise.

New features tested with i486 systems based on the Intel Saturn and
a DEC 4channel Ethernet card only, but expected to work on most systems.

The option PCI_REMAP has been removed !

Submitted by:	Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
Stefan Eßer
3f624a0187 Removed misleading copyright note. This file contains just
definitions taken from the PCI specs. Part of them were typed
in by Wolfgang Stanglmeier, the (at that time unneeded) rest
by Charles Hannum (thanks !).
1995-02-02 22:01:40 +00:00
David Greenman
6398cf3113 Reapplied all of Stefan's changes. What a mess - the files were modified
and moved at the same time. This made it *very* difficult to fix the
revision log lossage that happend when the files were moved. SIGH.
1995-02-02 13:12:18 +00:00