713 Commits

Author SHA1 Message Date
Warner Losh
4fc94b98b1 Better description of this file 2010-07-15 21:56:45 +00:00
Jayachandran C.
068c7ecd98 Fix for 64 bit compilation.
RMI bootloader passes argv[] and envp[] as an array of 32 bit pointers.
Convert the pointers to correct pointer type before use.
2010-07-15 16:39:17 +00:00
Warner Losh
0a94adbf70 Move TLB definitions to tlb.h 2010-07-15 03:56:08 +00:00
Warner Losh
8ccfc6442d This file has been unused for a while now... 2010-07-15 03:36:50 +00:00
Warner Losh
9d1f4f86c5 Remove unused stuff from cpu.h.
Move inappropriate stuff in cpu.h elsewhere:
{s,g}et_intr_mask -> md_var.h
num_tlbentries -> tlb.h
Remove #define clockframe trapframe and fix clock, which was the only place
this was used.
All the rest of this stuff was unused.

# we're not quite minimal yet, since we duplicate a few status register things
# here...

Inspired by: bde@
2010-07-15 01:58:20 +00:00
Warner Losh
fde8aa4e5c We don't need sys/cdefs.h for __CONCAT here. 2010-07-15 01:55:28 +00:00
Warner Losh
3e2b3b68d2 Remove i386-ish sysctls. Also, make the bootinfo sysctl OID_AUTO. 2010-07-15 01:53:17 +00:00
Warner Losh
b82b0cb2b1 Remove one layer of indirection. No need to call cpu_throw which then
calls mips_cpu_call via an obfuscated assembler call.  Instead, delete
the current cpu_throw, and rename mips_cpu_throw to cpu_throw.  This
is nicer to the cache on each context switch (since fixed jumps can be
prefected, while jumps through a register can't).  Incidentally, it
also saves about 5 or 6 instructions.

Reviewed by:	jmallet@
2010-07-15 01:47:47 +00:00
Warner Losh
b995e62fd0 Use cpuregs.h spellings over the cpu.h spellings. 2010-07-14 00:52:29 +00:00
Warner Losh
209e9e4670 Remove the unused part of cpu.h now that the rest of the tree has been
transitioned to use cpuregs.h spellings.  Now we're only 4x too big,
according to the bde-ometer.
2010-07-14 00:47:37 +00:00
Warner Losh
cded61cee5 Prefer the cpuregs.h spellings of register and bit names over cpu.h. 2010-07-14 00:41:22 +00:00
Warner Losh
396bf45a4f union cpuprid is also unused now 2010-07-13 22:36:45 +00:00
Warner Losh
7367e9351f Add INFO config register from mips32/64 land 2010-07-13 22:35:09 +00:00
Warner Losh
d3dbb44345 Remove redunant machine/cpuregs.h include.
Also, spell things like in machine/cpuregs.h instead of machine/cpu.h.
2010-07-13 22:30:27 +00:00
Warner Losh
a3a61c6ab4 Temp hack to N32 kernel: turn off debugger since n32 is too weird for ddb 2010-07-13 22:27:19 +00:00
Warner Losh
916c639557 Define break value for ddb.
Use int32/intptr casts for exception vector names.
Define MIPS_SR_INT_MASK again
Change MIPS_XKPHYS_CCA_* to MIPS_CCA_* since we can use them in many contexts
Minor gratuitous whitespace churn
2010-07-13 17:24:30 +00:00
Warner Losh
f0e521cc9c Use the cpuregs.h spellings for these registers rather than the cpu.h
spelling.
2010-07-13 17:21:15 +00:00
Warner Losh
035fb27d6a cpu_id and fpu_id are unused, except to be set early in the boot code.
The problem with setting it there is that the last CPU to come up
wins, it seems.  This also removes one more ifdef in locore.S, a noble
goal too.  Since they are unused, and pollute cpu.h, remove them.

Submitted by:	bde.h (cpu.h pollution)
Approved in theory by: jmallet@
2010-07-13 15:29:37 +00:00
Warner Losh
5a6cada275 Remove obsolete define "COPY_SIGCODE". This is unused in FreeBSD.
Submitted by:	bde@
2010-07-13 15:01:36 +00:00
Jayachandran C.
a9f2d68389 Merge jmallett@'s n64 work into HEAD
Initial set of ddb changes to support n64

Reviewed by:	imp
Obtained from:	jmallett (http://svn.freebsd.org/base/user/jmallett/octeon)
2010-07-12 10:22:58 +00:00
Jayachandran C.
160f3477ee Merge jmallett@'s n64 work into HEAD.
Merge changes for initial n64 support in pmap.c. Use direct mapped (XKPHYS)
access for a lot of operations that earlier needed temporary mapping. Add
support for using XKSEG for kernel mappings.

Reviewed by:	imp
Obtained from:	jmallett (http://svn.freebsd.org/base/user/jmallett/octeon)
2010-07-12 09:38:44 +00:00
Jayachandran C.
d204450e8d Merge jmallett@'s n64 work into HEAD
64 bit TLB definitions in pte.h

Reviewed by:	imp
Obtained from:	jmallett (http://svn.freebsd.org/base/user/jmallett/octeon)
2010-07-12 07:42:42 +00:00
Jayachandran C.
c15f697768 Move KSEG address definitions from cpu.h to cpuregs.h with the other
definitions, add some  XKPHYS related definitions for n64.

Reviewed by:	imp
2010-07-12 07:24:40 +00:00
Jayachandran C.
9132d3f5b0 Fix XLR64, the previous version had the contents of file duplicated. 2010-07-08 16:11:06 +00:00
Jayachandran C.
d580a6708b 64 bit ld script for mips, and configuration file for 64 bit compilation
on XLR

Approved by:	rrs
2010-07-08 16:06:58 +00:00
Jayachandran C.
35a69e02a4 Use 64 bit type for rqb_word_t in n64 kernel.
Reviewed by:	imp
Approved by:	rrs
2010-07-08 15:37:16 +00:00
Jayachandran C.
1f13150705 Enable KX bit, which is needed for 64 bit access, in status register
for XLR. Update exception handlers and other functions which set/change
status registers to preserve this.

Approved by:	rrs
2010-07-08 15:22:46 +00:00
Adrian Chadd
ff97a64735 Add TX-path aligned/unaligned stats for if_arge. 2010-07-08 15:20:57 +00:00
Jayachandran C.
5574a166c9 64 bit compilation support XLR platform code.
Mostly changes to make casting between int and pointer and printing
64bit values safe for 32 and 64 bit compile.

Approved by:	rrs
2010-07-08 15:05:23 +00:00
Adrian Chadd
ef54d27641 Address PR kern/148307 - fix if_ath TX mbuf alignment/size constraint checks
The existing code only checked the alignment of the first mbuf and
didn't enforce the size constraints.

This commit introduces a simple function to check the alignment and
size of all mbufs in the list. This fixes the initial issue in the
PR.

PR: kern/148307
Reviewed by: gonzo@
2010-07-08 14:59:32 +00:00
Jayachandran C.
76780f208c Fix minor issue in sys/mips/mips/cache_mipsNN.c, using int type for
virtual addr will break on 64 bit, change to vm_offset_t.

Reviewed by:	imp@
Approved by:	rrs (mentor)
2010-07-08 14:56:42 +00:00
Jayachandran C.
44fa0bf256 Merge jmallett@'s n64 work into HEAD - changeset 8
Updated PTE/PDE macros from http://svn.freebsd.org/base/user/jmallett/octeon
Introduce pmap_segshift() macro, use pmap_segmap() in place of pmap_pde, and
remove pmap_pde().

Approved by:	rrs (mentor)
Obtained from:	jmallett@
2010-07-08 14:49:55 +00:00
Adrian Chadd
d06458f7f7 Introduce a sysctl block for if_arge and, for now, a blank debug sysctl
placeholder for later.

Add in a missing FreeBSD ID string.
2010-07-08 14:34:15 +00:00
Adrian Chadd
ac35b90587 Fix the CS line definitions. These bits are for the CS2/CS1 lines
rather than CS1/CS0.

This has been tested on the Ubiqiti Routerstation Pro board.
2010-07-07 15:05:44 +00:00
Jayachandran C.
70b0d39bbc Add support for XLS 108 chips - update board.c/board.h to setup GMAC
driver parameters correctly.

Approved by:	rrs (mentor)
Obtained from:	Sriram Gorti <srgorti@netlogicmicro.com>
2010-07-02 13:30:26 +00:00
Jayachandran C.
2972a649c6 Remove save/restore of PageMask in tlb.c functions introduced in r209243.
If we save/restore the PageMask, the value set by the bootloader will
persist, and will cause problems later in TLB exception handler.
This caused a crash in AR71xx boards.

Also fixes the EntryHi mask in pte.h

Reported by: Luiz Otavio O Souza <lists.br@gmail.com>
Tested by:   Luiz Otavio O Souza <lists.br@gmail.com>

Approved by:	rrs (mentor)
2010-07-02 12:01:46 +00:00
John Baldwin
fc0de8f0b6 Move prototypes for kern_sigtimedwait() and kern_sigprocmask() to
<sys/syscallsubr.h> where all other kern_<syscall> prototypes live.
2010-06-30 18:03:42 +00:00
Jayachandran C.
4fddb8ed6f Add linker script and configuration file for n32 kernel.
Approved by:	rrs (mentor)
2010-06-24 10:14:31 +00:00
Jayachandran C.
9fa0972cf9 Merge jmallett@'s n64 work into HEAD - changeset 7
Initial support for n32 and n64 ABIs from
http://svn.freebsd.org/base/user/jmallett/octeon

Changes are:
 - syscall, exception and trap support for n32/n64 ABIs
 - 64-bit address space defines
 - _jmp_buf for n32/n64
 - casts between registers and ptr/int updated to work on n32/n64

Approved by:	rrs(mentor), jmallett
2010-06-24 08:08:43 +00:00
Adrian Chadd
7107f92fd6 Comment about the shared pins I know about. 2010-06-24 05:17:21 +00:00
Jayachandran C.
78fe0672b6 Merge jmallett@'s n64 work into HEAD - changeset 6
PTE flag cleanup from http://svn.freebsd.org/base/user/jmallett/octeon
- Rename PTE_xx flags to match their MIPS names
- Use the new pte_set/test/clear macros uniformly, instead of a mixture
  of mips_pg_xxx(), pmap_pte_x() macros and direct access.
- Remove unused macros and defines from pte.h and pmap.c

Discussed on freebsd-mips@

Approved by:	rrs(mentor), jmallett
2010-06-23 19:42:01 +00:00
Adrian Chadd
e3ded4845c AR71XX GPIO register definitions.
Reviewed by:	gonzo@
2010-06-23 03:59:26 +00:00
Adrian Chadd
7bc1af9566 Extend the AR71XX watchdog debugging and data.
* Add some per-device sysctl entries which record the watchdog state -
  whether it is armed; whether the last reboot was due to the watchdog.
* Add a per-device sysctl debug flag to enable logging watchdog arming/
  disarming.

Reviewed by:	gonzo@
2010-06-19 12:12:39 +00:00
Jayachandran C.
eac058828b Add support for newer XLS chips/boards in the GMAC driver.
Improved processor id code in board.h, remove unnecessary macros.

Approved by:	rrs(mentor)
2010-06-18 21:40:32 +00:00
Jayachandran C.
89b6177335 Merge jmallett@'s n64 work into HEAD - changeset 5
Remove unnecessary locking and sched_pin() call while creating a temporary
mapping.

Changes from http://svn.freebsd.org/base/user/jmallett/octeon

Approved by:	rrs (mentor), jmallett
2010-06-18 20:07:30 +00:00
Jayachandran C.
34da911965 Merge jmallett@'s n64 work into HEAD - changeset 4
Re-write tlb operations in C with a simpler API.
Update callers to use the new API.

Changes from http://svn.freebsd.org/base/user/jmallett/octeon

Approved by:	rrs(mentor), jmallett
2010-06-17 05:03:01 +00:00
Alan Cox
9124d0d6a3 Relax one of the new assertions in pmap_enter() a little. Specifically,
allow pmap_enter() to be performed on an unmanaged page that doesn't have
VPO_BUSY set.  Having VPO_BUSY set really only matters for managed pages.
(See, for example, pmap_remove_write().)
2010-06-11 15:49:39 +00:00
Alan Cox
ce18658792 Reduce the scope of the page queues lock and the number of
PG_REFERENCED changes in vm_pageout_object_deactivate_pages().
Simplify this function's inner loop using TAILQ_FOREACH(), and shorten
some of its overly long lines.  Update a stale comment.

Assert that PG_REFERENCED may be cleared only if the object containing
the page is locked.  Add a comment documenting this.

Assert that a caller to vm_page_requeue() holds the page queues lock,
and assert that the page is on a page queue.

Push down the page queues lock into pmap_ts_referenced() and
pmap_page_exists_quick().  (As of now, there are no longer any pmap
functions that expect to be called with the page queues lock held.)

Neither pmap_ts_referenced() nor pmap_page_exists_quick() should ever
be passed an unmanaged page.  Assert this rather than returning "0"
and "FALSE" respectively.

ARM:

Simplify pmap_page_exists_quick() by switching to TAILQ_FOREACH().

Push down the page queues lock inside of pmap_clearbit(), simplifying
pmap_clear_modify(), pmap_clear_reference(), and pmap_remove_write().
Additionally, this allows for avoiding the acquisition of the page
queues lock in some cases.

PowerPC/AIM:

moea*_page_exits_quick() and moea*_page_wired_mappings() will never be
called before pmap initialization is complete.  Therefore, the check
for moea_initialized can be eliminated.

Push down the page queues lock inside of moea*_clear_bit(),
simplifying moea*_clear_modify() and moea*_clear_reference().

The last parameter to moea*_clear_bit() is never used.  Eliminate it.

PowerPC/BookE:

Simplify mmu_booke_page_exists_quick()'s control flow.

Reviewed by:	kib@
2010-06-10 16:56:35 +00:00
Alan Cox
c99b7cc5c9 Don't set PG_WRITEABLE in init_pte_prot() (and thus pmap_enter()) unless
the page is managed.

Don't set the machine-independent layer's dirty field for the page being
mapped in init_pte_prot().  (The dirty field is only supposed to set when
a mapping is removed or write-protected and the page was managed and
modified.)

Determine whether or not to perform dirty bit emulation based on whether
or not the page is managed, i.e., pageable, not based on whether the page
is being mapped into the kernel address space.  Nearly all of the kernel
address space consists of unmanaged pages, so this has neglible impact on
the overhead of dirty bit emulation for the kernel address space.  However,
there can also exist unmanaged pages in the user address space.  Previously,
dirty bit emulation was unnecessarily performed on these pages.

Tested by:	jchandra@
2010-06-06 06:07:44 +00:00
Jayachandran C.
17dca144a2 Make vm_contig_grow_cache() extern, and use it when vm_phys_alloc_contig()
fails to allocate MIPS page table pages.  The current usage of VM_WAIT in
case of vm_phys_alloc_contig() failure is not correct, because:

"There is no guarantee that any of the available free (or cached) pages
after the VM_WAIT will fall within the range of suitable physical
addresses.  Every time this function sleeps and a single page is freed
(or cached) by someone else, this function will be reawakened.  With
a little bad luck, you could spin indefinitely."

We also add low and high parameters to vm_contig_grow_cache() and
vm_contig_launder() so that we restrict vm_contig_launder() to the range
of pages we are interested in.

Reported by: alc

Reviewed by:	alc
Approved by:	rrs (mentor)
2010-06-04 06:35:36 +00:00