Commit Graph

29 Commits

Author SHA1 Message Date
Rafal Jaworowski
7ec5aa41ca Introduce SheevaPlug support.
- The device is based on Marvell 88F6281 system on chip.
  - More info about the platform at http://www.plugcomputer.org

  - To build the FreeBSD kernel:
    make buildkernel TARGET_ARCH=arm KERNCONF=SHEEVAPLUG

  - Installation notes at: http://wiki.freebsd.org/FreeBSDMarvell

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 10:09:25 +00:00
Rafal Jaworowski
c0d853f6b9 Exclude common Kirkwood settings so they can be shared among various platforms
based on this SOC. This is a preliminary step for SheevaPlug support.

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 09:39:11 +00:00
Rafal Jaworowski
5694b144c0 Properly handle initial state of power mgmt.
Modules on Marvell SOC can be selectively PM-disabled, and we must not access
disabled devices' registers (attempt to initialize them) unconditionally, as
this leads to the system hang. This patch introduces graceful handling of the
PM state during devices init.

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 09:35:50 +00:00
Rafal Jaworowski
a7817ce466 Eliminate platform_pmap_init() to simplify Marvell bootstrap code. 2009-08-25 09:30:03 +00:00
Rafal Jaworowski
f981547c99 Map DPCPU pages into ARM kernel VA space.
DPCPU area was not properly mapped into kernel VA space, which caused page
fault on the first DPCPU access. This patch fixes the problem by mapping DPCPU
area into kernel VA space.

Submitted by:	Michal Hajduk, Piotr Ziecik
Reviewed by:	cognet, stas
Approved by:	re (kib)
Obtained from:	Semihalf
2009-07-01 20:07:44 +00:00
Rafal Jaworowski
ebeaf70342 Enable all populated TWSI (I2C) controllers on Marvell SOCs.
Obtained from:	Semihalf
2009-06-25 10:03:51 +00:00
Rafal Jaworowski
9d02143909 Introduce ata(4) support for Marvell integrated SATA controllers (found on
88F5xxx, 88F6xxx and MV78xxx system on chip devices).

Reviewed by:	stas
Obtained from:	Semihalf
2009-06-24 15:41:18 +00:00
Jeff Roberson
50c202c592 Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
   DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
   PCPU_*.  Requires only one extra instruction more than PCPU_* and is
   virtually the same as __thread for builtin and much faster for shared
   objects.  DPCPU variables can be initialized when defined.
 - Modules are supported by relocating the module's per-cpu linker set
   over space reserved in the kernel.  Modules may fail to load if there
   is insufficient space available.
 - Track space available for modules with a one-off extent allocator.
   Free may block for memory to allocate space for an extent.

Reviewed by:    jhb, rwatson, kan, sam, grehan, marius, marcel, stas
2009-06-23 22:42:39 +00:00
Marcel Moolenaar
85fc5c3b93 Move the memory layout definitions and logic from mvreg.h to mvwin.h
so that it isn't exposured unless needed. In particular this means
that it's easier to tune the memory layout based on board details.
While here, remove inclusion of <machine/intr.h> from mvreg.h. This
also contains exposure to SoC specifics in MI drivers, because NIRQ
depends on the SoC.
2009-06-12 20:00:38 +00:00
Andriy Gapon
08d43f8e62 strict kobj signatures: number of fixes for arm architecture
no functional changes should result

Reviewed by:	imp, current@
Approved by:	jhb (mentor)
2009-06-11 17:05:13 +00:00
Marcel Moolenaar
272489fe59 Pass the previously returned IRQ back to arm_get_next_irq() so that
the implementation can guarantee forward progress in the event of
a stuck interrupt or interrupt storm. This is especially critical
for fast interrupt handlers, as they can cause a hard hang in that
case. When first called, arm_get_next_irq() is passed -1.

Obtained from:	Juniper Networks, Inc.
2009-06-09 18:18:41 +00:00
Rafal Jaworowski
bc26e2e38f Adjust Marvell Discovery (MV78xxx) support to recognize newest chip revisions,
handle Z0 revision (early silicon) explicitly due to its quirks.

Obtained from:	Marvell, Semihalf
2009-04-16 11:20:18 +00:00
Andrew Thompson
68e3d00d68 Fix path and config name for ehci_mbus.c 2009-02-24 23:30:52 +00:00
Marcel Moolenaar
78c0a9c9e2 Include Marvell EHCI HC driver for USB2. 2009-02-16 21:42:41 +00:00
Rafal Jaworowski
4e883c81d0 Check PCIE link status before accessing the bus.
Some 88F5182-based systems (Linkstation) have problems when PCIE is
accessed without any peripherals present.
2009-01-09 12:38:41 +00:00
Rafal Jaworowski
bc54686d20 Rename Marvell ARM CPU specific file according to r186933. 2009-01-09 10:55:33 +00:00
Rafal Jaworowski
e7be09420c Improve Marvell SOCs PCI/PCIE driver.
- Provide dedicated rmans for MEM and IO resources.

- Convert PCI IRQ routing info into a table (from callback approach), provide
  config data for alternative DB- boards.

- Fix a wrong boundary check error in pcib_mbus_init_bar()

Obtained from:	Semihalf
2009-01-09 10:20:51 +00:00
Rafal Jaworowski
673c4fe419 Improve and extend Marvell SOCs platform code.
- Allow for setting per platform MPP/GPIO configuration in the kernel, so
  that we can override all settings firmware might set.

- Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR.

- Improve handling of USB controllers so that all port are available on the
  given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of
  USB decode windows set-up.

- Other minor fixes and cosmetics.

Obtained from:	Semihalf
2009-01-08 18:31:43 +00:00
Rafal Jaworowski
aba47c3f81 Minor style(9) corrections. 2009-01-08 13:25:22 +00:00
Rafal Jaworowski
4a0180a3b2 Adjust Marvell SOC support for A0 chip revision.
- Clean up TCLK handling so that it's dynamically recognized depending on
  registers settings or chip version/revision. Update registers definitions.

- Teach SOC ident routine about A0 (initial silicon version for general
  audience)

Obtained from:	Marvell, Semihalf
2009-01-08 13:20:28 +00:00
Rafal Jaworowski
b09d6bf325 Avoid confusion and adjust link address range of Marvell Orion kernel so it is
the same as for Kirkwood and Discovery.
2008-12-05 15:31:51 +00:00
Rafal Jaworowski
fe3ea17045 Fix configuration of the PCI bridge. This got omitted in the initial import of
this code.
2008-12-05 15:27:28 +00:00
Stanislav Sedov
129c518d68 - Fix spelling error in comments.
PR:		arm/128891
Submitted by:	Pavel Pankov <pankov_p@mail.ru>
Approved by:	kib (mentor)
2008-12-01 10:16:25 +00:00
Rafal Jaworowski
a715909b3e Improve error handling in pcib_mbus_identify(). 2008-11-19 17:07:01 +00:00
Rafal Jaworowski
e33d259975 Improve style(9) and other cosmetics in Marvell SOCs code. 2008-11-19 11:57:16 +00:00
Rafal Jaworowski
b4ef1cb7e8 Fix off-by-one error in mbus_attach(). 2008-11-19 11:49:35 +00:00
Rafal Jaworowski
6975124c23 PCI/PCI-Express support for Marvell systems.
Obtained from:	Marvell, Semihalf
2008-11-19 11:30:44 +00:00
Rafal Jaworowski
71f00bea66 Auto-size kernel page tables allocation on Marvell systems.
This allows mini dumps to fully work for these platforms.

Obtained from:	Juniper Networks, Semihalf
2008-11-06 16:25:12 +00:00
Rafal Jaworowski
373bbe25ff Introduce basic support for Marvell families of system-on-chip ARM devices:
*  Orion
     - 88F5181
     - 88F5182
     - 88F5281

  * Kirkwood
     - 88F6281

  * Discovery
     - MV78100

The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:

  * GPIO
  * Interrupt controller
  * L1, L2 cache
  * Timers, watchdog, RTC
  * TWSI (I2C)
  * UART

Other peripherals drivers will be introduced separately.

Reviewed by:	imp, marcel, stass (Thanks guys!)
Obtained from:	Marvell, Semihalf
2008-10-13 20:07:13 +00:00