possible future I-cache coherency operation can succeed. On ARM
for example the L1 cache can be (is) virtually mapped, which
means that any I/O that uses temporary mappings will not see the
I-cache made coherent. On ia64 a similar behaviour has been
observed. By flushing the D-cache, execution of binaries backed
by md(4) and/or NFS work reliably.
For Book-E (powerpc), execution over NFS exhibits SIGILL once in
a while as well, though cpu_flush_dcache() hasn't been implemented
yet.
Doing an explicit D-cache flush as part of the non-DMA based I/O
read operation eliminates the need to do it as part of the
I-cache coherency operation itself and as such avoids pessimizing
the DMA-based I/O read operations for which D-cache are already
flushed/invalidated. It also allows future optimizations whereby
the bcopy() followed by the D-cache flush can be integrated in a
single operation, which could be implemented using on-chips DMA
engines, by-passing the D-cache altogether.
register 0x52, not ctrl1. This appears to be a mistake in the bcm
reverse engineering page, and has been corrected there. Tracing
through the code, this is more in keeping with the "documented"
register. Sephe thinks it looks interesting and may be worth
fixing. :)
Submitted by: ddkprog at yahoo com
Reviewed by: Sepherosa Ziehau
- In bce_rx_intr(), use BUS_DMASYNC_POSTREAD instead of
BUS_DMASYNC_POSTWRITE, as we want to "read" from the
rx page chain pages.
- Document why we need to do PREWRITE after we have updated
the rx page chain pages.
- In bce_intr(), use BUS_DMASYNC_POSTREAD and
BUS_DMASYNC_PREREAD when before and after CPU "reading"
the status block.
- Adjust some nearby style mismatches/etc.
Pointed out by: yongari
Approved by: davidch (no objection) but bugs are mine :)
# Note: The driver doesn't support either these PHY types, so this is
# effectively a nop.
Submitted by: "ddk"
Obtained from: http://paradox.lissyara.su/bwi.diff
believe it was a BCM4319. However, it is the a/b/g variation of the
BCM4318. The chip itself is labelled BCM4318EKFBG, and the board is
BCM94318MKABG.
Paradox's patch includes the type of 802.11 wireless for each card,
but changes all the names (I don't think the latter is quite right).
Import that part of the patch, but keep the current set of BCM names
(with a minor tweak for the 4306 ones). I'll need to verify them via
some other means.
Obtained from: http://paradox.lissyara.su/bwi.diff (partially)
Apart from the 16 virtual terminals, Syscons allocates two device nodes
that should not really be TTYs, even though they are. One of them is
consolectl. In RELENG_7 and before, these device nodes are used in
single user mode. After I simplified input path, we only use this device
node to call ioctl() on (moused, Xorg, vidcontrol).
When you call ioctl() on consolectl, it will behave the same as being
called on the first window.
drops and re-grabs the softc mutex in the middle, resulting in kernel
trap 12. This may happen when a lot of traffic is being hammered on
one bge(4) interface while the system is shutting down.
Reported by: Alexander Sack <pisymbol gmail com>
PR: kern/134548
MFC After: 2 weeks
chipset-specific code to attach chipset-specific data.
- Use chipset-specific data in the acard and promise chipsets rather than
changing the ivars of ATA PCI devices. ivars are reserved for use by the
parent bus driver and are _not_ available for use by devices directly.
This fixes a panic during sysctl -a with certain Promise controllers with
ACPI enabled.
Reviewed by: mav
Tested by: Magnus Kling (kingfon @ gmail) (on 7)
MFC after: 3 days
NULL or change it. We initialize it before we set if_ioctl. It can
therefore never be NULL, and most other drivers don't bother with this
sanity check.
