572ab50c54
9 Commits
| Author | SHA1 | Message | Date | |
|---|---|---|---|---|
Justin T. Gibbs
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2cd3cc377a |
aic79xx.c:
Include read streaming in the PPR flags we display in diagnostics. In ahd_reset(), set the known mode after our initial pause prior to setting the mode. We can't just set the mode directly because the current mode, after the pause, is most likely unknown and setting the mode when the saved mode is unknown will trigger an assertion in the mode debug code. Complete an audit for SCB RAM reads. These reads must be performed via the special ahd_in?_scbram() methods so we can perform a Rev A. PCI-X workaround. Remove a superfluous mode save operation that was performed just prior to a call to ahd_clear_critical_section(). The saved mode was never restored and wouldn't have been valid anyway since the mode could change while single stepping out of a critical section. aic79xx.h: Add new BUG definition AHD_PCIX_SCBRAM_RD_BUG. aic79xx_inline.h: Update ahd_inb_scbram routine to check for AHD_PCIX_SCBRAM_RD_BUG and only apply the workaround if this bug is active. The old code applied the workaround in all cases. aic79xx_pci.c: Set AHD_PCIX_SCBRAM_RD_BUG for the A4. Remove an attempted saved_modes call in ahd_pci_test_register_access(). Saving the modes can only occur when we are paused, but the call was happening before the chip was known to be paused. Restoring the modes doesn't make sense either since the code makes no assumptions about the state of the sequencer until the first time the mode is set by the driver. This happens after the registers are successfully mapped. |
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Justin T. Gibbs
|
acae33b029 |
aic79xx.c:
Clear the LQICRC_NLQ status should it pop up after we have already handled the SCSIPERR. During some streaming operations this status can be delayed until the stream ends. Without this change, the driver would complain about a "Missing case in ahd_handle_scsiint". In the LQOBUSFREE handler... Don't return the LQOMGR back to the idle state until after we have cleaned up ENSELO and any status related to this selection. The last thing we need is the LQO manager starting another select-out before we have updated the execution queue. It is not clear whether the LQOMGR would, or would not start a new selection early. Make sure ENSELO is off prior to clearing SELDO by flushing device writes. Move assignment of the next target SCB pointer inside of an if to make the code clearer. The effect is the same. Dump card state in both "Unexpected PKT busfree" paths. In ahd_reset(), set the chip to SCSI mode before reading SXFRCTL1. That register only exists in the SCSI mode. Also set the mode explicitly to the SCSI mode after chip reset due to paranoia. Re-arrange code so that SXFRCTL1 is restored as quickly after the chip reset as possible. S/G structurs must be 8byte aligned. Make this official by saying so in our DMA tag. Disable CIO bus stretch on MDFFSTAT if SHVALID is about to come true. This can cause a CIO bus lockup if a PCI or PCI-X error occurs while the stretch is occurring - the host cannot service the PCI-X error since the CIO bus is locked out and SHVALID will never resolve. The stretch was added in the Rev B to simplify the wait for SHVALID to resolve, but the code to do this in the open source sequencer is so simple it was never removed. Consistently use MAX_OFFSET for the user max syncrate set from non-volatile storage. This ensures that the offset does not conflict with AH?_OFFSET_UNKNOWN. Have ahd_pause_and_flushwork set the mode to ensure that it has access to the registers it checks. Also modify the checking of intstat so that the check against 0xFF can actually succeed if the INT_PEND mask is something other than 0xFF. Although there are no cardbus U320 controllers, this check may be needed to recover from a hot-plug PCI removal that occurs without informing the driver. Fix a typo. sg_prefetch_cnt -> sg_prefetch_align. This fixes an infinite loop at card initialization if the cacheline size is 0. aic79xx.h: Add AHD_EARLY_REQ_BUG bug flag. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. Change AH?_OFFSET_UNKNOWN to 0xFF. This is a value that the curr->offset can never be, unlike '0' which we previously used. This fixes code that only checks for a non-zero offset to determine if a sync negotiation is required since it will fire in the unknown case even if the goal is async. aic79xx.reg: Add comments for LQISTAT bits indicating their names in the 7902 data book. We use slightly different and more descriptive names in the firmware. Fix spelling errors. Include the CDB's length just after the CDB pointer in the DMA'ed CDB case. aic79xx.seq: Update comments regarding rundown of the GSFIFO to reflect reality. Fix spelling errors. Since we use an 8byte address and 1 byte length, shorten the size of a block move for the legacy DMA'ed CDB case from 11 to 9 bytes. Remove code that, assuming the abort pending feature worked, would set MK_MESSAGE in the SCB's control byte on completion to catch invalid reselections. Since we don't see interrupts for completed selections, this status update could occur prior to us noticing the SELDO. The "select-out" queue logic will get confused by the MK_MESSAGE bit being set as this is used to catch packatized connections where we select-out with ATN. Since the abort pending feature doesn't work on any released controllers yet, this code was never executed. Add support for the AHD_EARLY_REQ_BUG. Don't ignore persistent REQ assertions just because they were asserted within the bus settle delay window. This allows us to tolerate devices like the GEM318 that violate the SCSI spec. Remove unintentional settnig of SG_CACHE_AVAIL. Writing this bit should have no effect, but who knows... On the Rev A, we must wait for HDMAENACK before loading additional segments to avoid clobbering the address of the first segment in the S/G FIFO. This resolves data-corruption issues with certain IBM (now Hitachi) and Fujitsu U320 drives. Rearrange calc_residual to avoid an extra jmp instruction. On RevA Silicon, if the target returns us to data-out after we have already trained for data-out, it is possible for us to transition the free running clock to data-valid before the required 100ns P1 setup time (8 P1 assertions in fast-160 mode). This will only happen if this L-Q is a continuation of a data transfer for which we have already prefetched data into our FIFO (LQ/Data followed by LQ/Data for the same write transaction). This can cause some target implementations to miss the first few data transfers on the bus. We detect this situation by noticing that this is the first data transfer after an LQ (LQIWORKONLQ true), that the data transfer is a continuation of a transfer already setup in our FIFO (SAVEPTRS interrupt), and that the transaction is a write (DIRECTION set in DFCNTRL). The delay is performed by disabling SCSIEN until we see the first REQ from the target. Only compile in snapshot savepointers handler for RevA silicon where it is enabled. Handle the cfg4icmd packetized interrupt. We just need to load the address and count, start the DMA, and CLRCHN once the transfer is complete. Fix an oversight in the overrun handler for packetized status operations. We need to wait for either CTXTDONE or an overrun when checking for an overrun. The previous code did not wait and thus could decide that no overrun had occurred even though an overrun will occur on the next data-valid req. Add some comment to this section for clarity. Use LAST_SEG_DONE instead of LASTSDONE for testing transfer completion in the packetized status case. LASTSDONE may come up more quickly since it only records completion on the SCSI side, but since LAST_SEG_DONE is used everywhere else (and needs to be), this is less confusing. Add a missing invalidation of the longjmp address in the non-pack handler. This code needs additional review. aic79xx_inline.h: Fix spelling error. aic79xx_osm.c: Set the cdb length for CDBs dma'ed from host memory. Add a comment indicating that, should CAM start supporting cdbs larger than 16bytes, the driver could store the CDB in the status buffer. aic79xx_pci.c: Add a table entry for the 39320A. Added a missing comma to an error string table. Fix spelling errors. |
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Justin T. Gibbs
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0794987d01 |
aic79xx.c:
Implement the SCB_SILENT flag. This is useful for
hushing up the driver during DV or other operations
that we expect to cause transmission errors. The
messages will still print if the SHOW_MASKED_ERRORS
debug option is enabled.
Save and restore the NEGOADDR address when setting
new transfer settings. The sequencer performs lookups
in the negotiation table too and it expects NEGOADDR
to remain consistent across pause/unpause sessions.
Consistently use "offset" instead of "period" to determine
if we are running sync or not.
Add a SHOW_MESSAGES diagnostic for when we assert ATN
during message processing.
Print out IU, QAS, and RTI features when showing transfer options.
Limit the syncrate after all option conformance
changes have taken place in ahd_devlimited_syncrate.
Changes in options may change the final syncrate we
accept.
Keep a copy of the hs_mailbox in our softc so that
we can perform read/modify/write operations on the
hs_mailbox without having to pause the sequencer to
read the last written value. Use the ENINT_COALESS
flag in the hs_mailbox to toggle interrupt coalessing.
Add entrypoints for enabling interrupt coalessing and
setting both a timeout (how long to wait for commands
to be coalessed) and a maximum commands to coaless value.
Add a statistics timer that decides when to enable or
disable interrupt coalessing based on load.
Add a routine, ahd_reset_cmds_pending() which is used
to update the CMDS_PENDING sequencer variable whenever
error recovery compeltes SCBs without notifying the
sequencer. Since ahd_reset_cmds_pending is called
during ahd_unpause() only if we've aborted SCBs, its
call to ahd_flush_qoutfifo should not cause recursion
through ahd_run_qoutfifo(). A panic has been added to
ensure that this recursion does not occur.
In ahd_search_qinfifo, update the CMDS_PENDING sequencer
variable directly. ahd_search_qinififo can be called
in situations where using ahd_reset_cmds_pending() might
cause recursion. Since we can safely determine the
exact number to reduce CMDS_PENDING by in this scenario
without running the qoutfifo, the manual update is sufficient.
Clean up diagnostics.
Add ahd_flush_qoutfifo() which will run the qoutfifo
as well as complete any commands sitting on the
sequencer's COMPLETE_SCB lists or the good status FIFO.
Use this routine in several places that did similar
things in an add-hoc, but incomplete, fashion. A call
to this routine was also added to ahd_abort_scbs() to
close a race.
In ahd_pause_and_flushwork() only return once selections
are safely disabled. Flush all completed commands via
ahd_flush_qoutfifo().
Remove "Now packetized" diagnostic now that this
information is incorperated into the actual negotiation
messages that are displayed.
When forcing renegotiation, don't clober the current
ppr_options. Much of the driver uses this information
to determine if we are currently packetized or not.
Remove some stray spaces at column 1 in ahd_set_tags.
When complaining about getting a host message loop
request with no pending messages, print out the
SCB_CONTROL register down on the card.
Modify the ahd_sent_msg() routine to handle a search
for an outgoing identify message. Use this to detect
a msg reject on an identify message which typically
indicates that the target thought we were packetized.
Force a renegotiation in this case.
In ahd_search_qinfifo(), wait more effectively for SCB
DMA activities to cease. We also disable SCB fetch
operations since we are about to change the qinfifo
and any fetch in progress will likely be invalidated.
In ahd_qinfifo_count(), fix the qinfifo empty case.
In ahd_dump_card_state(), print out CCSCBCTL in the
correct mode.
If we are a narrow controller, don't set the current
width to unknown when forcing a future negotiation.
This just confuses the code into attempting a wide
negotiation on a narrow bus.
Add support for task management function completions.
Modify ahd_handle_devreset so that it can handle
lun resets in addition to target resets. Use
ahd_handle_devreset for lun and target reset task
management functions.
Handle the abort task TMF race case better. We now
wait until any current selections are over and then
set the TMF back to zero. This should cause the sequencer
to ignore the abort TMF completion should it occur.
Correct a bug in the illegal phase handler that
caused us to drop down to narrow when handling the
unexpected command phase case after 3rd party
reset of a packetized device.
Indicate the features, bugs, and flags set in the softc
that are used to control firmware patch download when
booting verbose.
aic79xx.h:
Add coalessing and HS_MAILBOX fields.
Add per-softc variables for the stats "daemon".
Add a debug option for interrupt coalessing activities.
Add two new softc flags:
o AHD_UPDATE_PEND_CMDS
Run ahd_reset_cmds_pending() on the next unpause.
o AHD_RUNNING_QOUTFIFO
Used to catch recursion through ahd_run_qoutfifo().
aic79xx.reg:
Correct register addresses related to the software timer
and the DFDBCTL register.
Add constants paramaterizing the software timer.
Add scratch ram locations for storing interrupt coalessing
tunables.
Break INTMASK in SEQITNCTL out into INTMASK1 and INTMASK2.
In at least the REV A, these are writable bits. We make
use of that for a swtimer workaround in the sequencer.
Since HS_MAILBOX autoclears, provide a sequencer variable
to store its contents.
Add SEQINT codes for handling task management completions.
aic79xx.seq:
Correct ignore wide residue processing check for
a wide negotiation being in effect. We must be
in the SCSI register window in order to access the
negotiation table.
Use the software timer and a commands completed count to
implement interrupt coalessing. The command complete is
deferred until either the maximum command threshold or a
the expiration of a command deferral timer. If we have
more SCBs to complete to the host (sitting in COMPLETE_SCB
lists), always try to coaless them up to our coalessing limit.
If coalessing is enabled, but we have fewer commands oustanting
than the host's min coalessing limit, complete the command
immediately.
Add code to track the number of commands outstanding.
Commands are outstanding from the time they are placed
into the execution queue until the DMA to post completion
is setup.
Add a workaround for intvec_2 interrupts on the H2A4.
In H2A4, the mode pointer is not saved for intvec2, but
is restored on iret. This can lead to the restoration
of a bogus mode ptr. Manually clear the intmask bits and
do a normal return to compensate. We use intvec_2 to
track interrupt coalessing timeouts.
Since we cannot disable the swtimer's countdown, simply
mask its interrupt once we no longer care about it firing.
In idle_loop_cchan, update LOCAL_HS_MAILBOX everytime
we are notified of an HS_MAILBOX update via the
HS_MAILBOX_ACT bit in QOFF_CTLSTA. We have to use a
local copy of persistant portions of the HS_MAILBOX as
the mailbox auto-clears on any read.
Move the test for the cfg4istat interrupt up an instruction
to hopefully close a race between the next outgoing selection
and our disabling of selections.
Add a missing ret to the last instruction in load_overrun_buf.
Add notifications to the host of task management
completions as well as the completions for commands
that completed successfully before their corresponding
TMF could be sent.
Hold a critical section during select-out processing
until we have a fully identified connection. This
removes a race condition with the legacy abort handler.
Correct a few spelling errors in some comments.
aic79xx_inline.h:
Call ahd_reset_cmds_pending() in ahd_unpause if required.
Update cmdcmplt interrupt statistics in our interrupt
handler.
Allow callers to ahd_send_scb() to set the task management
function.
aic79xx_pci.c:
Disable SERR and pause the controller prior to performing
our mmapped I/O test. The U320 controllers do not support
"auto-access-pause".
aic79xx_osm.c:
Set the task management function now that
ahd_send_scb() doesn't do it for us. We
also perform a lun reset in response to BDR
requests to packetized devices.
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Scott Long
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0c5aa4c57b |
Major update to the ahd driver to fix many bugs found in the previous
version, plus add support for the new features found in the Rev B version of the chip. The changelog is quite long and can be provided on request. Major features include vastly improved protocol violation handling, full support for the 7902 Rev B, better parity error handling, and better packetized overrun handling, to name a few. Approved by: re (blanket) |
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Justin T. Gibbs
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c59c8a72cf |
Upgrade to version 1.1 of the aic79xx U320 driver.
aic79xx.c: o Remove redundant ahd_update_modes() call. o Correct panic in diagnostic should state corruption cause the SCB Id to be invalid during a selection timeout. o Add workaround for missing BUSFREEREV feature in Rev A silicon. o Corect formatting nits. o Use register pretty printing in more places. o Save and restore our SCB pointer when updating the waiting queue list for an "expected" LQ-out busfree. o In ahd_clear_intstat, deal with the missing autoclear in the CLRLQO* registers. o BE fixup in a diagnostic printf. o Make sure that we are in the proper mode before disabling selections in ahd_update_pending_scbs. o Add more diagnostics. o task_attribute_nonpkt_tag -> task_attribute: we don't need a nonpkt_tag field anymore for allowing all 512 SCBs to be used in non-packetized connections. o Negotiate HOLD_MCS to U320 devices. o Add a few additional mode assertions. o Restore the chip mode after clearing out the qinfifo so that code using ahd_abort_scbs sees a consistent mode. o Simplify the DMA engine shutdown routine prior to performing a bus reset. o Perform the sequencer restart after a chip reset prior to setting up our timer to poll for the reset to be complete. On some OSes, the timer could actually pre-empt us and order is important here. o Have our "reset poller" set the expected mode since there is no guarantee of what mode will be in force when we are called from the OS timer. o Save and restore the SCB pointer in ahd_dump_card_state(). This routine must not modify card state. o Ditto for ahd_dump_scbs(). aic79xx.h: o Add a few more chip bug definitions. o Align our tag on a 32bit boundary. aic79xx.reg: aic79xx.seq: o Start work on removing workarounds for Rev B. o Use a special location in scratch from for stroring our SCBPTR during legacy FIFO allocations. This corrects problems in mixed packetized/non-packetized configurations where calling into a FIFO task corrupted our SCBPTR. o Don't rely on DMA priority to guarantee that all data in our FIFOs will flush prior to a command completion notification going out of the command channel. We've never seen this assumption fail, but better safe than sorry. o Deal with missing BUSFREEREV feature in H2A. o Simplify disconnect list code now that the list will always have only a single entry. o Implement the AHD_REG_SLOW_SETTLE_BUG workaround. o Swith to using "REG_ISR" for local mode scratch during our ISR. o Add a missing jmp to the data_group_dma_loop after our data pointers have been re-initialized by the kernel. o Correct test in the bitbucket code so that we actually wait for the bitbucket to complete before signaling the kernel of the overrun condition. o Reposition pkt_saveptrs to avoid a jmp instruction. o Update a comment to reflect that the code now waits for a FIFO to drain prior to issuing a CLRCHN. aic79xx_inline.h: o Remove unused untagged queue handling code. o Don't attempt to htole64 what could be a 32bit value. aic79xx_pci.c: o Set additional bug flags for rev A chips. |
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Scott Long
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7a55322993 | Use the correct bit value for a debug options | ||
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Justin T. Gibbs
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544c53b8be |
Updates for new non-packetized SCB-ID collision avoidance,
busy target table addressing changes, our qoufifo scheme, and long lun support. Drop bus reset hold delay to 25us. Remove chip workarounds for revisions that never went to production. Add aic7901A identification information. Remove untagged queue logic. |
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Justin T. Gibbs
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cdd49e97b4 | Hook up the ahd driver. | ||
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Justin T. Gibbs
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17d2475554 |
Enter the ahd driver which supports the Adaptec AIC7902 Ultra320, PCI-X
SCSI Controller chip. |