I backed-out the changes in -current and didn't touch stable at all (I
thought I had my patch order reversed, not what actually happened).
AIEEE! I can't even blame the crack for this one since I broke my
crack pipe a few weeks ago. I think sleep deprivation gets the blame
for this one.
Medal for noticing this one goes to: Jim Bloom <bloom@acm.org>
the new PnP code. Since the bulk of the driver changes are not being
committed at this time, it will not affect the driver. The code is being
committed early to allow others synchronise changes.
new system is integrated with the ISA bus code more cleanly and allows
the future addition of more enumerators such as PnPBIOS and ACPI.
This commit also enables the new pcm driver since it is somewhat tied to
the new PnP code.
Fix a bug where video capture locks up on channel changes.
Many thanks to Juha for solving this.
Submitted by: Juha Nurmela <Juha.Nurmela@quicknet.inet.fi>
Remove WD formatting code which has never worked in 386bsd or FreeBSD.
Remove DIOCSSTEP and DIOCSRETRIES ioctls as well, they belong in
history, along with the SMD disks.
OK'ed by: bde
* Make it possible to type a filename to boot1 so that it is possible to
recover from fatally broken versions of /boot/loader.
* Make a start at a CD boot program (not yet functional).
make -jN fail. This fixes the present problem only, not the larger one
of when those internal tools are built and the cross-compiling etc.
Submitted by: luoqi
bringing in DHCP support. The only thing I left out were Poul-Henning's
newfs changes since I'm not sure if he's brought the rest of that support
into -stable yet. If it turns out that this is the case, I'll MFC those
changes too.
external NatSemi PHY chip was programmed to respond to MII address 24.
In the 3c905B ASICs, the transceiver is internal but it's still mapped
to MII address 24. But *some* 3Com 3c905B ASIC revisions map the
transceiver control registers to *all* MII addresses (0 through 31).
The miibus code probes for PHYs at all MII addresses and because of
this unusual behavior, it will attempt to map the same PHY registers
several times over, which doesn't work.
Naturally, the 3c905B NIC that I tested happened not to exhibit this
behavior.
The fix is to tweak xl_miibus_readreg() and xl_miibus_writereg()
to only respond when attempting to read from MII address 24. This
is safe to do since the 3Com documentation indicates that the PHY
and/or internal transceiver will always be mapped to address 24,
and there are no 3Com XL NICs with more than one PHY.
