off chip that was on one prototype board. However, this appears to be
a design that many chipsets are compatible with its PPEC register set
(eg the Omega 82c094). Through the kindness of the Red Hat developer
David Woodhouse, I now have this datasheet.
I may take the advise of one of the bsd-nomads (whose name
unfortunately escapes me at the moment) and split out all these 16-bit
I/O mapped PCI devices into a separate driver...
that it has one BAR that's mapped to 0x3e0 and is I/O only. It does
not conform to the Yenta spec, like other PCI PCMICA bridges do (eg
the TI 1031, which is mostly a 1131 w/o 32bit card support). It
appears that this chip may also need to not route PCI interrupts
as well.
This chip is used in the NEC Versa 2430CD (and it appears that
sometimes it works, while other times it doesn't) and others in the
2400 series. While the NEC website claims Cardbus support, I can't figure
out how that is possible.
Submitted by: Ben Timby <ben@webexc.com>
- clean up wakeup routing fixup code by using macros.
- allocate pte object temporary for kernel thread to avoid kernel
panic by events from sleep button or lid switch.
value (-1) in lue of 50 (which assumes a 5.0V card). The rest of the
pccard system doesn't detect the proper voltage for the card, so we have
to do it on powerup. Many (all?) 3.3V cards can tolerate 5.0V for reading
the CIS, but may fail to operate properly when so powered.
Idea from: Chiharu Shibata-san <chi@bd.mbn.or.jp> in bsd-nomads:15867
kern.post.mk.
# this should allow us to move kern.post.mk to the last line of the makefiles,
# but I'll do that slowly as I verify that one can do that w/o breaking things.
Submitted by: naddy
Any modifications to SYSTEM_OBJS after including kern.post.mk
will not make it to SYSTEM_DEP and consequently any dependency
rules. This caused __{div|rem}* to not be built...
It doesn't help us catch overflowing vector entries at compile time.
Instead use the .org directive. The last entry in the IVT doesn't
strictly need to be limited to 256 bytes, but doing so allows the
the VHPT to be placed immediately following the IVT without wasting
any space due to alignment.
as being valid. Previously only the magic number and the virtual
address were checked, but it makes little sense to require that
the virtual address is the same (the message buffer is located at
the end of physical memory), and checks on the msg_bufx and msg_bufr
indices were missing.
Submitted by: Bodo Rueskamp <br@clabsms.de>
Tripped over during a kernel debugging tutorial given by: grog
Reviewed by: grog, dwmalone
MFC after: 1 week
on a vnode-backed object must be incremented *after* obtaining the vnode
lock. If it is bumped before obtaining the vnode lock we can deadlock
against vtruncbuf().
Submitted by: peter, ps
MFC after: 3 days
* Re-organise RID allocation so that we don't accidentally give a RID
to two different processes. Also randomise the order to try to reduce
collisions in VHPT and TLB. Don't allocate RIDs for regions which are
unused.
* Allocate space for VHPT based on the size of physical memory. More
tuning is needed here.
* Add sysctl instrumentation for VHPT - see sysctl vm.stats.vhpt
* Fix a bug in pmap_prefault() which prevented it from actually adding
pages to the pmap.
* Remove ancient dead debugging code.
* Add DDB commands for examining translation registers and region
registers.
The first change fixes the 'free/cache page %p was dirty' panic which I
have been seeing when the system is put under moderate load. It also
fixes the negative RSS values in ps which have been confusing me for a
while.
With this set of changes the ia64 port is reliable enough to build its
own kernels, even with a 20-way parallel build. Next stop buildworld.
o Bite the bullet and create controller types for the 6729 and also for
the 673x. Rename the 672x to 6722.
o Define minimal extended register info (just register 0xa for reading VS[12]).
# I think the last version may have broken 673x controllers, but this should
# fix them.
Tested on the 6722, but not the 6729.
Ideas from: Chiharu Shibata-san's article in bsd-nomads:15866
on my CL-PD6722, but won't work on the CL-PD6729. The latter two need
more sophisticated detection of 3.3V cards than I'm up to at the
moment. Also, only a few of the ISA chipsets that support 3.3V will
likely work at the moment.
It appears that for 3.3V cards we must detect them and adjust the
pwr.vcc value from 50 to 33. Give a strong hint to automatically
power up the card for PD_POWER cards.
This makes my SMC 2602W (the 3.3V version of the 2632W) work on my
Fujitsu Stylistic 500.
SMC 3.3V card donated by: Ryan Losh
Thanks to: bsd-nomads for reviews of past 3.3V code
Basically FIFOs become a real pain to abuse as a rendevous point without
this change because you can't really select(2) on them because they always
return ready even though there is no writer (to signal EOF).
Obtained from: BSD/os
sysctl_req', which describes in-progress sysctl requests. This permits
sysctl handlers to have access to the current thread, permitting work
on implementing td->td_ucred, migration of suser() to using struct
thread to derive the appropriate ucred, and allowing struct thread to be
passed down to other code, such as network code where td is not currently
available (and curproc is used).
o Note: netncp and netsmb are not updated to reflect this change, as they
are not currently KSE-adapted.
Reviewed by: julian
Obtained from: TrustedBSD Project
