Commit Graph

30 Commits

Author SHA1 Message Date
gibbs
6534e32f7d Add PCIR_CAP_PTR as a define for the location of the capability
pointer of type 0 devices.  This is required by my last aic7xxx change.
2000-12-20 14:36:52 +00:00
msmith
c3cf005c4b Next round of PCI subsystem updates:
- Break out the /dev/pci driver into a separate file.
 - Kill the COMPAT_OLDPCI support.
 - Make the EISA bridge attach a bit more like the old code; explicitly
   check for the existence of eisa0/isa0 and only attach if they don't
   already exist.  Only make one bus_generic_attach() pass over the
   bridge, once both busses are attached.  Note that the stupid Intel
   bridge's class is entirely unpredictable.
 - Add prototypes and re-layout the core PCI modules in line with
   current coding standards (not a major whitespace change, just moving
   the module data to the top of the file).
 - Remove redundant type-2 bridge support from the core PCI code; the
   PCI-CardBus code does this itself internally.  Remove the now
   entirely redundant header-class-specific support, as well as the
   secondary and subordinate bus number fields.  These are bridge
   attributes now.
 - Add support for PCI Extended Capabilities.
 - Add support for PCI Power Management.  The interface currently
   allows a driver to query and set the power state of a device.
 - Add helper functions to allow drivers to enable/disable busmastering
   and the decoding of I/O and memory ranges.
 - Use PCI_SLOTMAX and PCI_FUNCMAX rather than magic numbers in some
   places.
 - Make the PCI-PCI bridge code a little more paranoid about valid
   I/O and memory decodes.
 - Add some more PCI register definitions for the command and status
   registers.  Correct another bogus definition for type-1 bridges.
2000-12-13 01:25:11 +00:00
msmith
3246f521da - We have access to our own device_t here, so use pci_read_config
rather than finding our parent pcib and using its PCI_READ_CONFIG
   method.

 - Fix the defines for the 32-bit I/O decode registers, and properly
   process the 16-bit versions.  Now we will correctly check that I/O
   resources behind the bridge are going to be decoded.

 - Bring the quirk for the Orion PCI:PCI bridge in here (since it
   seems to want to set the secondary/supplementary bus numbers).

 - Use PCI_SLOTMAX rather than a magic number.
2000-12-12 13:20:35 +00:00
archie
bc3a00b59c Add definition for PCIS_SERIALBUS_SMBUS PCI device subclass.
Remove cut & paste leftovers.
2000-10-02 00:41:43 +00:00
gibbs
30ccffb914 Add PCIM_CMD_MWRICEN, the bit in the command register in PCI space
that enables memory write and invalidate cycles on a bus master.
2000-09-16 20:06:13 +00:00
peter
eda3ab6536 Encapsulate the old PCI compatability support and APIs completely under
"options COMPAT_OLDPCI".  This option already existed, but now also tidies
up the declarations in #include <pci/pci*.h>.  It is amazing how much stuff
was using the old pre-FreeBSD 3.x names and going silently undetected.
2000-05-28 16:35:57 +00:00
yokota
847df92358 Added PCIR_BIOS (0x30). 2000-01-10 12:53:19 +00:00
peter
6b8112e41c Add the 16550 programming interface code for PCIS_SIMPLECOMM_UART. 1999-10-09 16:00:56 +00:00
peter
3b842d34e8 $Id$ -> $FreeBSD$ 1999-08-28 01:08:13 +00:00
peter
087d4857e5 Bring the 'new-bus' to the i386. This extensively changes the way the
i386 platform boots, it is no longer ISA-centric, and is fully dynamic.
Most old drivers compile and run without modification via 'compatability
shims' to enable a smoother transition.  eisa, isapnp and pccard* are
not yet using the new resource manager.  Once fully converted, all drivers
will be loadable, including PCI and ISA.

(Some other changes appear to have snuck in, including a port of Soren's
 ATA driver to the Alpha.  Soren, back this out if you need to.)

This is a checkpoint of work-in-progress, but is quite functional.

The bulk of the work was done over the last few years by Doug Rabson and
Garrett Wollman.

Approved by:	core
1999-04-16 21:22:55 +00:00
gibbs
c3bd7bdfdd ahc_pci.c:
Disable DPARCKEN in the DSCOMMAND0 register on the aic7890/91/96/97.
	Parity checking is broken for some chip/MB combinations and this
	is the work around recommended by Adaptec.

dpt_pci.c:
	Remove a superflous '{' that prevented DPT_ALLOW_MEMIO from working.

pcireg.h:
	Add a definition for Parity Error Reponse bit in the PCI Space
	command register.
1998-10-07 03:40:51 +00:00
dyson
82185efa23 Addition of support of the slightly rogue Promise IDE interface(Dyson), support
of multiple PCI IDE controllers(Dyson), and some updates and cleanups from
John Hood, who originally made our IDE DMA stuff work :-).

I have run tests with 7 IDE drives connected to my system, all in DMA
mode, with no errors.  Modulo any bugs, this stuff makes IDE look
really good (within it's limitations.)

Submitted by:	John Hood <cgull@smoke.marlboro.vt.us>
1997-09-20 07:41:58 +00:00
peter
81758d0374 PCI_CLASS_MASS_STORAGE (under PCI_COMPAT) was used in a driver in LINT
still (stallion.c).
1997-06-01 16:00:43 +00:00
se
9764a899d5 Add one more compatibility define to make the Adaptec driver compile
with option AHC_ALLOW_MEMIO again ....
1997-05-28 20:37:19 +00:00
se
19f6360161 Define command register enable bits, which are required for a consitency
test added to pci_compat.c
1997-05-28 11:15:18 +00:00
se
cfea775806 Completely replace the PCI bus driver code to make it better reflect
reality. There will be a new call interface, but for now the file
pci_compat.c (which is to be deleted, after all drivers are converted)
provides an emulation of the old PCI bus driver functions. The only
change that might be visible to drivers is, that the type pcici_t
(which had been meant to be just a handle, whose exact definition
should not be relied on), has been converted into a pcicfgregs* .

The Tekram AMD SCSI driver bogusly relied on the definition of pcici_t
and has been converted to just call the PCI drivers functions to access
configuration space register, instead of inventing its own ...

This code is by no means complete, but assumed to be fully operational,
and brings the official code base more in line with my development code.

A new generic device descriptor data type has to be agreed on. The PCI
code will then use that data type to provide new functionality:

1) userconfig support
2) "wired" PCI devices
3) conflicts checking against ISA/EISA
4) maps will depend on the command register enable bits
5) PCI to Anything bridges can be defined as devices,
   and are probed like any "standard" PCI device.

The following features are currently missing, but will be added back,
soon:

1) unknown device probe message
2) suppression of "mirrored" devices caused by ancient, broken chip-sets

This code relies on generic shared interrupt support just commited to
kern_intr.c (plus the modifications of isa.c and isa_device.h).
1997-05-26 15:08:43 +00:00
se
96ee89db8a Add definition of PCI_SUBID_REG2, the subvendor/device ID for
a header type 2 device.
1997-04-24 08:03:31 +00:00
phk
1be613d0b3 The bit of the cardbus bridge support code se and I have been able to agree
on so far... :-)
Reviewed by:	se
1997-04-20 06:57:43 +00:00
peter
94b6d72794 Back out part 1 of the MCFH that changed $Id$ to $FreeBSD$. We are not
ready for it yet.
1997-02-22 09:48:43 +00:00
jkh
808a36ef65 Make the long-awaited change from $Id$ to $FreeBSD$
This will make a number of things easier in the future, as well as (finally!)
avoiding the Id-smashing problem which has plagued developers for so long.

Boy, I'm glad we're not using sup anymore.  This update would have been
insane otherwise.
1997-01-14 07:20:47 +00:00
se
d50c7b65af Add support for header type == 1 devices (PCI 2.1 compatible PCI to PCI
bridges with support for 64 bit memory addresses and 32 bit I/O addresses).

The code is not complete. It ignores the upper half of the long addresses.
This is not a problem on PC compatible systems, but has to be fixed for
real computers.
1996-11-12 23:18:12 +00:00
se
bb3b58af85 Fix PCI to PCI bridge register bit field masks.
Thanks to "Mike Durian" <durian@plutotech.com> for the very good
problem report and his support as a beta tester of this patch.
1996-11-12 23:10:24 +00:00
se
10f2cb3b34 Add support for ioctl() accesses to PCI config space registers.
Garrett Wollman sent me this code a few weeks ago for review, and I made
some significant changes, which he in turn accepted ...

In order to make use of these changes, a device entry has to added to /dev.

Submitted by:	wollman
1996-10-22 20:20:14 +00:00
se
45ff9914bf Add support for multi-function devices. 1996-01-25 18:32:00 +00:00
se
735dc86501 Fix bad typo: > was used instead of >> ...
Submitted by:	Matt Thomas <matt@lkg.dec.com>
1996-01-19 19:03:47 +00:00
se
6e667246cd Completely new PCI code:
1) Supports PCI to PCI bridge devices (and tries to initialise them,
   even if the BIOS is brain dead).
2) Supports shared PCI interrupts. Interrupt handlers now MUST return
   '0' if they found nothing to do, '1' otherwise.

New features tested with i486 systems based on the Intel Saturn and
a DEC 4channel Ethernet card only, but expected to work on most systems.

The option PCI_REMAP has been removed !

Submitted by:	Wolfgang Stanglmeier <wolf@kintaro.cologne.de>
1995-03-21 23:01:06 +00:00
se
af678f727c Removed misleading copyright note. This file contains just
definitions taken from the PCI specs. Part of them were typed
in by Wolfgang Stanglmeier, the (at that time unneeded) rest
by Charles Hannum (thanks !).
1995-02-02 22:01:40 +00:00
dg
57e383cd4c Reapplied all of Stefan's changes. What a mess - the files were modified
and moved at the same time. This made it *very* difficult to fix the
revision log lossage that happend when the files were moved. SIGH.
1995-02-02 13:12:18 +00:00
se
b7d81897fe Submitted by:
Added hooks for "lsdev" ...
PCI devices should need no individual code for lsdev.
1994-11-02 23:47:14 +00:00
se
2a7081fe01 Submitted by: Wolfgang Stanglmeier <wolf@dentaro.GUN.de>
Files merged and name change: pci_device.h + pcibios.h -> pcireg.h
1994-10-12 02:25:03 +00:00