Commit Graph

10 Commits

Author SHA1 Message Date
yongari
153b44ab56 Add HW MAC counter support for newer JMC250/JMC260 revisions. 2008-12-04 02:16:53 +00:00
yongari
20e7552f46 Add support for newer JMC250/JMC260 revisions.
o Chip full mask revision 2 or later controllers have to
   set correct Tx MAC and Tx offload clock depending on negotiated
   link speed.
 o JMC260 chip full mask revision 2 has a silicon bug that can't
   handle 64bit DMA addressing. Add workaround to the bug by
   limiting DMA address space to be within 32bit.
 o Valid FIFO space of receive control and status register was
   changed on chip full mask revision 2 or later controllers. For
   these controllers, use default 16QW as it's supposed to be the
   safest value for maximum PCIe compatibility. JMicron confirmed
   performance will not be reduced even if the FIFO space is set
   to 16QW.
 o When interface is put into suspend/shutdown state, remove Tx MAC
   and Tx offload clock to save more power. We don't need Tx clock
   at all in this state.
 o Added new register definition for chip full mask revision 2 or
   later controllers.

Thanks to JMicron for their continuous support of FreeBSD.
2008-12-04 01:58:40 +00:00
yongari
9645b4dc68 Make sure to read the last byte of EEPROM descriptor. Previously
the last byte of the ethernet address was not read which in turn
resulted in getting 5 out of the 6 bytes of ethernet address and
always returned ENOENT. I did not notice the bug on FPGA version
because of additional configuration data in EEPROM.

Pointed out by:	bouyer at NetBSD
2008-10-14 00:54:15 +00:00
yongari
2c490bb4c3 Read PCI device id instead of PCI revision id. Also checks the read
device id is JMC260 family. Previously it just verified the deivce
is JMC260 Rev A0. This will make it easy for newer JMC2xx support.

Pointed out by:	bouyer at NetBSD
2008-10-13 01:11:28 +00:00
yongari
514fd19ec3 Add workaround for occasional packet loss issue of JMC250 A2
when it runs on half-duplex media.
While I'm here add register definition for GPREG1. ATM the GPREG1
register is only valid for JMC250 A1/A2.

Submitted by:	Ethan at JMicron
2008-09-22 06:17:21 +00:00
yongari
f94dfca526 Add workaround for CRC errors seen at 100Mbps on JMC250 A2.
While here update chip revision number of JMC250/JMC260 from the
latest datasheet.
2008-09-09 10:19:48 +00:00
yongari
2dd7bef310 Fix typo. 2008-09-09 10:10:03 +00:00
yongari
d499ae8522 Fix buffer discard index.
While I'm here dicard all buffers if errored frame is part of
multi-segmented frames.

Pointed out by:	sephe
Reviewd by:	sephe
MFC after:	3 days
2008-07-28 02:37:15 +00:00
yongari
25c768ed0d Correct 1000Mbps link handling logic for JMC250. This should make
jme(4) run on 1000Mbps link.
2008-07-18 04:20:48 +00:00
yongari
1a8fa7ea7b Add driver support for PCIe adapters based on JMicron JMC250
gigabit ethernet and JMC260 fast ethernet controllers. ATM jme(4)
supports all hardware features except RSS and multiple Tx/Rx queue.

In these days most ethernet controller vendors take a ply of
concealing hardware detailes from open source developers. As
contrasted with these vendors JMicron provided all necessary
information needed to write a stable driver during driver writing
and answered many questions I had. They even helped fixing driver
bugs with protocol analyzer. Many thanks to JMicron for their
support of FreeBSD.

H/W donated by:	JMicron
2008-05-27 01:42:01 +00:00