3 Commits

Author	SHA1	Message	Date
Jayachandran C.	d5d4261f35	Update memory and resource allocation code for SoC devices ... The XLP on-chip devices have PCI configuration headers, but some of the devices need custom resource allocation code. - devices with no MEM/IO BARs with registers in PCIe extended reg space have to be handled in memory resource allocation - devices without INTPIN/INTLINE in PCI header can be supported by having these faked with a shadow register. - Some devices does not allow 8/16 bit access to the register space, he default bus space cannot be used for these. Subclass pci and override attach and resource allocation methods to take care of this. Remove earlier code which did this partially.	2012-03-27 15:39:55 +00:00
Jayachandran C.	cd4c8d64ff	MIPS XLP platform code update. ... * Update the hardware access register definitions and functions to bring them in line with other Netlogic software. * Update the platform bus to use PCI even for on-chip devices. Add a dummy PCI driver to ignore on-chip devices which do not need driver. * Provide memory and IRQ resource allocation code for on-chip devices which cannot get it from PCI config. * add support for on-chip PCI and USB interfaces. * update conf files, enable pci and retain old MAXCPU until we can support >32 cpus. Approved by: re(kib), jmallett	2011-09-05 10:45:29 +00:00
Jayachandran C.	4d91ecaf4c	Add MIPS platform files for Netlogic XLP SoC. ... Processor, UART, PIC and Messaging Network code. Also add sys/mips/nlm/hal for on-chip device registers. In collaboration with: Prabhath Raman <prabhathpr at netlogicmicro com> Approved by: bz(re), jmallett, imp(mips)	2011-07-16 19:35:44 +00:00