like the args to the config space accessors these functions replaced.
This reduces the likelyhood of overflow when the args are used in
macros on the alpha. This prevents memory management faults when
probing the pci bus on sables, multias and nonames.
Approved by: dfr
Tested by: Bernd Walter <ticso@cicely8.cicely.de>
- Use ACPI_PHYSICAL_ADDRESS
- RSDT -> XSDT
- FACP -> FADT
- No APIC table support
- Don't install a global EC handler; this has bad side-effects
(it invokes _REG in *all* EC spaces in the namespace!)
- Check for PCI bus instances already existing before adding them
but a hack! Add `flags 0x8000' to the psm driver to enable it.
The psm driver will try to get out of out-of-sync situation
by disabling the mouse and immediately enable it again.
If you are seeing this out-of-sync problem because of an
incompetent(?!) KVM switch, this hack will NOT be good
for you. However, if you are occasionally seeing the
problem because of lost mouse interrupt, this might help.
4) The cardbus CIS code treats the CIS_PTR as a mapping register if
it is mentioned in the CIS. I don't have a spec handy to understand
why the CIS_PTR is mentioned in the CIS, but allocating a memory range
for it is certainly bogus. My patch ignores bar #6 to prevent the
mapping.
[The pccard spec says that BAR 0 and 7 (-1 and 6 in thic case since we
did a minus one) is "reserved". The off by 1 error has been fixed.
also bar=5 is invalid for IO maps, so we check it.]
5) The CIS code allocated duplicate resources to those already found
by cardbus_add_resources(). The fix is to pass in the bar computed
from the CIS instead of the particular resource ID for that bar,
so bus_generic_alloc_resource succeeds in finding the old resource.
[fixed, also removed superfluous (and incorrect) writing back to the
PCI config space.]
7) The CIS code seems to use the wrong bit to determine rather a particular
register mapping is for I/O or memory space. From looking at the
two cards I have, it seems TPL_BAR_REG_AS should be 0x10 instead
of 0x08. Otherwise, all registers that should be I/O mapped gain
a second mapping in memory space.
[Oops, the spec does say 0x10..., fixed]
Submitted by: Justin Gibbs
Fix amr_map_command so that 40LD-specific commands get the scatter-gather
list count in the right place. I don't understand why AMI did it like
this, but now the AMI MegaManager can talk to the newer (1600 and later)
controllers.
Remove an unused variable.
Include <machine/clock.h> when necessary.
Tweak some debugging levels to make things more intelligible.
io or memory space access enabled. This patch defers the setting
of these bits until after all of the mapping registers are probed.
It might be even better to defer this until a particular mapping
is activated and to disable that type of access when a new
register is activated.
2) The PCI spec is very explicit about how mapping registers and
the expansion ROM mapping register should be probed. This patch
makes cardbus_add_map() follow the spec.
3) The PCI spec allows a device to use the same address decoder for
expansion ROM access as is used for memory mapped register access.
This patch carefully enables and disables ROM access along with
resource (de)activiation.
This doesn't include the prefetching detection stuff (maybe later when code is written to actually turn on prefetching). It also does not use the PCI definitions (yet, I'll try to put this in all at once later)
Submitted by: Justin T. Gibbs
- Make pccbb/cardbus kld loadable and unloadable.
- Make pccbb/cardbus use the power interface from pccard instead of inventing its own.
- some other minor fixes
call instead.
This makes a pretty dramatic difference to the amount of work that
the harvester needs to do - it is much friendlier on the system.
(80386 and 80486 class machines will notice little, as the new
get_cyclecounter() call is a wrapper round nanotime(9) for them).
the interface to use callout_* instead of timeout(). Also add an
IS_MPSAFE #define (currently off) which will mark the driver as mpsafe
to the upper layers.
before adding/removing packets from the queue. Also, the if_obytes and
if_omcasts fields should only be manipulated under protection of the mutex.
IF_ENQUEUE, IF_PREPEND, and IF_DEQUEUE perform all necessary locking on
the queue. An IF_LOCK macro is provided, as well as the old (mutex-less)
versions of the macros in the form _IF_ENQUEUE, _IF_QFULL, for code which
needs them, but their use is discouraged.
Two new macros are introduced: IF_DRAIN() to drain a queue, and IF_HANDOFF,
which takes care of locking/enqueue, and also statistics updating/start
if necessary.
using a cardbus based system with pccbb providing the pcic interface).
Something isn't quite right.. when the driver allocates and activates
its resources, the IO space that was requested reads as all zeros (versus
the original 0xff's as it normally is when there is no device responding).
Also, deactivate the resources before releasing them. OLDCARD doesn't
seem to care but NEWCARD/CARDBUS get rather unhappy if you release
a resource that hasn't been deactivated yet.
Make pcic_p.c only compile with oldcard kernels.
instead of ng_send_data().
The latter could lead to running the IP stack at splimp
instead of splnet, (among other problems) (that MAY be safe
but I wouldn't count on it).
Noticed while preparing a new set of netgraph stuff.
This makes crash recovery work for stripe sizes that are not multiples of
DEFAULT_REVIVE_BLOCKSIZE (currently 64 kB).
While we're here, fix a few cosmetic nits.
Reviewed by: grog
Sponsored by: Enitel ASA (http://www.enitel.no/)
of the data structures to include new members that weren't defined in the
manual I have.
I opted to use Doug Ambrisko's WEP patches since David Cornejo's patches
did not include the necessary changes to ancontrol(8) to actually enable
and use WEP.
NOTE: I don't currently have access to an Aironet card, so I can't test
any of this. Everything compiles and close scrutiny doesn't reveal any
obvious problems, but Murphy's Law applies. This means I will probably
leave these changes in -current for a bit longer than usual until I'm
sure they work right.
This allows us to successfully attach early Storage Dimension cards.
Allocate mailboxes for the 742A bellow the 16MB limit. Although these
cards seem to be able to deal with all other types of data anywhere
in a 32bit address space, 24bit addresses are required for mailboxes.
bt_eisa.c:
Add device IDs for all Storage Dimension products I could
find from their web site.
Thanks to Ted Mittelstaed for loaning me the equipment to diagnose
and fix these problems.
