Commit Graph

16 Commits

Author SHA1 Message Date
Juli Mallett
5f3173b517 o) Fix XKPHYS physical address extraction. Also define cache coherency
attributes for XKPHYS.
o) Make coprocessor 0 accessor function macros for register+selector registers
   take the full name so that e.g. (as done in this commit), prid selector 1
   can be written through mips_wr_ebase() rather than mips_wr_prid1().
o) Allow for sign extension of 32-bit segment addresses.
o) Remove an unused MIPS-I register number.
2010-04-19 06:01:58 +00:00
Juli Mallett
b6777295a6 o) Add SMP support for Octeon using U-Boot to launch all the processors at the
same time.
o) Remove some unused trivial uart functions from octeon_machdep now that the
   uart part is fully working and they are unused.
o) Use __func__ instead of __FUNCTION__.
o) Use intr_*() instead of other routines that do the same thing.
o) Remove some duplicate printfs from the Octeon port, as well as duplicate
   setting of Maxmem.
o) Use the right frequency divider on Octeon.
o) Use PCPU_GET(cpuid) consistently to get the cpuid of the running core.
o) Remove some unused macros in the Octeon port.
o) Use mips_sync() around use of the global dpcpu, whose value may not be
   visible to APs at first.
o) When loading the first thread's stack, use macros to make the code correct
   for n64 as well.
o) Remove stub, do-nothing FAU init/enable/disable functions from the RGMX
   driver.
2010-04-17 03:08:13 +00:00
Juli Mallett
9b98f51885 Don't force single user on Octeon anymore. 2010-03-11 22:25:53 +00:00
Juli Mallett
54e3435255 Properly detect a type of real board that claims to have a 0.0 revision.
This fixes at least memory detection on that board.

Sponsored by:	Packet Forensics
2010-03-05 22:46:11 +00:00
Warner Losh
a62e05a4e0 Make printfs work for both OCTEON1 and OCTEON1-32 2010-02-18 19:27:00 +00:00
Oleksandr Tymoshenko
f6951d3084 - Clean-up output of memory banks info 2010-02-16 00:08:42 +00:00
Warner Losh
dd8b9d6300 We make it to single user well, but not so well to multi-user. Force
single user for the moment since that's a better experience for people
trying this code out...
2010-01-28 20:39:50 +00:00
Warner Losh
3dae97d413 Doh. Remove extra pcpu initialization that I thought was needed, but
isn't needed since we moved all that into mips_pcpu0_init.
2010-01-26 02:39:14 +00:00
Warner Losh
e7f82fbbaf o Write the soft reset bit in the cavium core to reset. [1]
o panic if the board boot descriptor is too old...

Obtained from:	[1] looking at the cavium sdk's executive code
2010-01-24 18:05:38 +00:00
Warner Losh
2069a5911e Eliminate octeonregs.h. It was a copy of maltaregs.h with
s/malta/octeon/gi done...
2010-01-23 06:42:47 +00:00
Warner Losh
8c019fbaa9 Migrate from old "DDB" style debugger to newer KDB style. 2010-01-23 00:24:31 +00:00
Warner Losh
f92a1e9b89 o Add support for memory above 256MB on the octeon.
o Force the ebase to be 0x80000000 (the base that we're booted with may
  need to be respected in the future).
o Initialize the clock early so we can initialize the console early
o use panic where we can now use it.
o Tag some code for parsing the boot records as belonging in the cavium sdk.
o remove support for booting on ancient boards...

# we make it further in bootstrapping now: interrupts being enabled in the
# uarts are now taking us out, it seems, for reasons unknown.
2010-01-22 20:40:07 +00:00
Warner Losh
5f04b82bcc Don't clear bss/sbss. The boot loader already does this. In addition,
the Cavium version of the boot loader puts data just after &end, so
our rounding up to the next page in clearing memory overwrote their
data, which meant we'd get a lot of wrong values for parameters to the
system.

While I'm here, remove argc/argv parsing.  Those values aren't passed
in via a0 and a1, so it was a guaranted panic on some boards.
2010-01-22 09:23:34 +00:00
Warner Losh
24e4f4a84d Jump to the mips reset vector. OR in the 0x80000000 for kseg0 and
cast it to a long so it will work on 64-bit targets.

reset now works on octeon, so I don't have to power cycle the board as
often.
2010-01-22 09:19:57 +00:00
Warner Losh
a6ec986223 Cope with the move and if_timer going way. 2010-01-11 04:29:26 +00:00
Warner Losh
6b06709221 Merge from projects/mips to head by hand:
Copy the support files for the Octeon 1 CPU from sys/mips/octeon1 on
the projects/mips side to sys/mips/cavium on the head side to conform
to the other vendor code.  This code was contributed by Cavium to the
project and forward ported by Warner Losh, with some additional code
from Randal Stewart.

# I'll fix the building problems the move creates in a future commit.
2010-01-09 18:59:03 +00:00