All armv6 processors are plenty fast enough for HZ=1000.
No changes are made for older arm systems, because some chips are a bit
wimpy for 1000 while others do fine, so it has to be set on a per-config
basis.
boards.
This is just intended to split the common config entries out, further
cleanup is expected.
Reviewed by: ian@, rpaulo@ (earlier version)
Differential Revision: https://reviews.freebsd.org/D731
in effect due to r250753. That is sufficient for all SoCs with a 32 byte
cache line size. Systems with 64 byte cache lines will need the option;
that will be done in a separate commit.
Thanks to loos@ for pointing out r250753.
this to the cache line size is required to avoid data corruption on armv4
and armv5, and improves performance on armv6, in both cases by avoiding
partial cacheline flushes for USB IO.
All these configs already exist in 10-stable. A few that don't (and
thus can't be MFC'd yet) will be committed separately.
