Previously, these cards were supported by the lnc driver (and they
still are, but the pcn driver will claim them first), which is fine
except the lnc driver runs them in 16-bit LANCE compatibility mode.
The pcn driver runs these chips in 32-bit mode and uses the RX alignment
feature to achieve zero-copy receive. (Which puts it in the same
class as the xl, fxp and tl chipsets.) This driver is also MI, so it
will work on the x86 and alpha platforms. (The lnc driver is still
needed to support non-PCI cards. At some point, I'll need to newbusify
it so that it too will me MI.)
The Am79c978 HomePNA adapter is also supported.
newbus for referencing device interrupt handlers.
- Move the 'struct intrec' type which describes interrupt sources into
sys/interrupt.h instead of making it just be a x86 structure.
- Don't create 'ithd' and 'intrec' typedefs, instead, just use 'struct ithd'
and 'struct intrec'
- Move the code to translate new-bus interrupt flags into an interrupt thread
priority out of the x86 nexus code and into a MI ithread_priority()
function in sys/kern/kern_intr.c.
- Remove now-uneeded x86-specific headers from sys/dev/ata/ata-all.c and
sys/pci/pci_compat.c.
re-enable interrupts when actually releasing the lock.
- Bring across some fixes to propagate_priority from the x86 code.
(It still doesn't work properly, however.)
- Use the SMTX state when putting a process that blocks on a mutex to sleep.
- Use mi_switch instead of cpu_switch so that accounting works properly as
well as other things.
- Bring across DDB protection of the spinlock timeout panic which is useful
in a multiple CPU system when 1 CPU enters the debugger holding the
sched_lock so that the other CPU doesn't panic as well resulting in all
sorts of fun things.
- Bring across various other small changes in format strings and comments
to sync up with the x86 code.
fixes a serious problem with the previous version where an input could
have been placed in the same register as an output which would stop
the inline from working properly.
* Redo atomic_{set,clear,add,subtract}_{32,64} as inlines since the code
sequence is shorter than the call sequence to the code in atomic.s.
I will remove the functions from atomic.s after a grace period to allow
people to rebuild kernel modules.
and mtx_exit(). This change tracks the i386 version.
Rename mtx_enter(), mtx_try_enter(), and mtx_exit() and wrap them with cpp
macros that expand to pass filename and line number information. This is
necessary since we're using inline functions instead of macros now.
Add const to the filename pointers passed througout the mtx and witness
code.
include:
* Mutual exclusion is used instead of spl*(). See mutex(9). (Note: The
alpha port is still in transition and currently uses both.)
* Per-CPU idle processes.
* Interrupts are run in their own separate kernel threads and can be
preempted (i386 only).
Partially contributed by: BSDi (BSD/OS)
Submissions by (at least): cp, dfr, dillon, grog, jake, jhb, sheldonh
machines. The patch uses an existing global variable in place of the
newbus accessor to get at use_bwx.
This is a quick fix to get miatas booting again; somebody
with more newbus skills than I can muster will have to correct it.
Matt Jacob's description of the problem from the -alpha list:
The IVAR accessor stuff for pcib is incompletely specified for CIA. There's
only one accessor defined, and that's to get the BUS instance number.
<..>
The device methods that try and get at the use_bwx get overriden because
there's only one ivar for CIA's pcib, and that's for hose #, and it's always
zero.
foo_pcib_[read|write]_config() functions rather than relying on
a break or return being in the CFG macro.
This fixes a panic later in the boot process on a UP1000. From
inspection, it looks like this fixes a similar problem in the tsunami code.
Approved by: dfr
the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
which call busspace.
* Rework pci config accesses to route through the pcib device instead of
calling a MD function directly.
With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.
