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14 Commits

Author SHA1 Message Date
marius
b484b97e77 For cheetah-class CPUs ensure that the dt512_0 is set to hold 8k pages 
for all three contexts and configure the dt512_1 to hold 4MB pages for
them (e.g. for direct mappings).
This might allow for additional optimization by using the faulting
page sizes provided by AA_DMMU_TAG_ACCESS_EXT for bypassing the page
size walker for the dt512 in the superpage support code.

Submitted by:	nwhitehorn (initial patch)
 2008-09-08 21:24:25 +00:00
marius
18594e5bbc cosmetic changes and style fixes 2008-08-13 20:30:28 +00:00
kmacy
98d1f51687 unbreak sparc64 loader build 
re-add accidentally deleted asi value
remove sun4v only header include

Approved by: rwatson (mentor)
Reviewed by: jmg
 2006-10-09 05:59:04 +00:00
kmacy
65e20bda09 kernel clean up to make the sun4v kernel build 
Reviewed by: jmg
Approved by: rwatson (mentor)
 2006-10-09 04:45:19 +00:00
marius
98a829e8ea Add convenience macros for the bits in ASI_ESTATE_ERROR_EN_REG (used 
for ECC handling) and the additional uses of the ASIs 0x77 and 0x7f
as well as their bits (used for a CPU bug workaround).

MFC after:	3 days
 2006-03-29 00:08:48 +00:00
tmm
0d2b3aeaaa Add ASI definitions of UltraSPARC-III (Cu) processors, and add some 
previously missing US-I and II ones.
 2002-07-16 16:22:25 +00:00
jake
ceb8ef47f2 Add asis for the upa config reg, which contains the hardware cpu id, and 
for the interrupt send register, which is used for dispatching ipis.
 2002-01-08 04:29:50 +00:00
tmm
30ac245755 Header file updates needed for the cache code: add/correct some ASI 
definitions and add PAGE_*_MIN and -_MAX macros.
 2001-11-09 19:37:52 +00:00
jake
e9a17647c3 The definition for ASI_IMMU_TAG_TARGET_REG was wrong. Sort. 2001-09-03 22:02:15 +00:00
jake
ed59961343 Add a definition for the load store unit control register. 2001-08-20 23:31:41 +00:00
jake
a9e7523870 Add asis for interrupt registers. 2001-08-10 04:17:29 +00:00
obrien
f202ead276 The author isn't a [UC] Regents. Correct the copyright language. 2001-08-09 02:09:34 +00:00
tmm
91c3a007e5 Add floating point context switching code for sparc64. 
Reviewed by:	jake
 2001-08-04 18:55:15 +00:00
jake
fb7edc502f Flesh out the sparc64 port considerably. This contains: 
- mostly complete kernel pmap support, and tested but currently turned
  off userland pmap support
- low level assembly language trap, context switching and support code
- fully implemented atomic.h and supporting cpufunc.h
- some support for kernel debugging with ddb
- various header tweaks and filling out of machine dependent structures
 2001-07-31 06:05:05 +00:00