Commit Graph

12 Commits

Author SHA1 Message Date
imp
15b870b9d9 Doh. Remove extra pcpu initialization that I thought was needed, but
isn't needed since we moved all that into mips_pcpu0_init.
2010-01-26 02:39:14 +00:00
imp
4ac34cbf90 Export knowledge of the special bus space we use for the console to
obio.  Take advantage of the fact that obio only really supports uart
at the moment to use the uart bus tag always for IOPORT allocations.

# this needs to be redone to conform to FreeBSD standards and allow for
# additional drivers for SoC hardware to attach
2010-01-25 19:27:20 +00:00
imp
894160498a Turn on debugging on the fpa unit. Fix some printfs that were only
enabled for debugging.  This should be turned off before we release,
but we need it for the moment.
2010-01-25 19:25:21 +00:00
imp
f02d63f346 o Write the soft reset bit in the cavium core to reset. [1]
o panic if the board boot descriptor is too old...

Obtained from:	[1] looking at the cavium sdk's executive code
2010-01-24 18:05:38 +00:00
imp
c88be204c7 Eliminate octeonregs.h. It was a copy of maltaregs.h with
s/malta/octeon/gi done...
2010-01-23 06:42:47 +00:00
imp
9ab59f4d1a Migrate from old "DDB" style debugger to newer KDB style. 2010-01-23 00:24:31 +00:00
imp
a3046a69ae Declare octeon_get_clock_rate, now exported from octeon_machdep 2010-01-22 20:44:34 +00:00
imp
3a7c404577 o Add support for memory above 256MB on the octeon.
o Force the ebase to be 0x80000000 (the base that we're booted with may
  need to be respected in the future).
o Initialize the clock early so we can initialize the console early
o use panic where we can now use it.
o Tag some code for parsing the boot records as belonging in the cavium sdk.
o remove support for booting on ancient boards...

# we make it further in bootstrapping now: interrupts being enabled in the
# uarts are now taking us out, it seems, for reasons unknown.
2010-01-22 20:40:07 +00:00
imp
1ccb8e2172 Don't clear bss/sbss. The boot loader already does this. In addition,
the Cavium version of the boot loader puts data just after &end, so
our rounding up to the next page in clearing memory overwrote their
data, which meant we'd get a lot of wrong values for parameters to the
system.

While I'm here, remove argc/argv parsing.  Those values aren't passed
in via a0 and a1, so it was a guaranted panic on some boards.
2010-01-22 09:23:34 +00:00
imp
299ddaaf43 Jump to the mips reset vector. OR in the 0x80000000 for kseg0 and
cast it to a long so it will work on 64-bit targets.

reset now works on octeon, so I don't have to power cycle the board as
often.
2010-01-22 09:19:57 +00:00
imp
03b840517d Cope with the move and if_timer going way. 2010-01-11 04:29:26 +00:00
imp
e50f5ca653 Merge from projects/mips to head by hand:
Copy the support files for the Octeon 1 CPU from sys/mips/octeon1 on
the projects/mips side to sys/mips/cavium on the head side to conform
to the other vendor code.  This code was contributed by Cavium to the
project and forward ported by Warner Losh, with some additional code
from Randal Stewart.

# I'll fix the building problems the move creates in a future commit.
2010-01-09 18:59:03 +00:00