Commit Graph

140 Commits

Author SHA1 Message Date
Emmanuel Vadot
1788e14d92 arm64: allwinner: Add CCU DE2
The Display Engine 2 have it's own Clock and Control Unit, add support
for it.
2019-03-07 19:30:37 +00:00
Emmanuel Vadot
7032095101 xhci_mv: Move the driver to generic_xhci
Marvell XHCI is in fact generic-xhci, so move the driver and
add the compatible string.
While here, get and enable the phy if the dtb provide one.
The xhci bindings state that phys should be in a 'phys' property but
Marvell DTS uses 'usb-phy', only add support for 'usb-phy' for now.

Sponsored-by:      Rubicon Communications, LCC ("Netgate")
2019-02-27 21:04:40 +00:00
Emmanuel Vadot
aa7c3aa6fa usb_nop_xceiv: Add support for this pseudo device
This is a "fake" phy that handle regulator, clocks and reset gpio.
Only clock and regulator is supported for now.

Sponsored-by:      Rubicon Communications, LCC ("Netgate")
2019-02-27 20:52:35 +00:00
Emmanuel Vadot
f6f8a42129 arm64: Fix compile when removing SOC_ROCKCHIP_* options
Make every rockchip file depend on the multiple soc_rockchip options
While here make rk_i2c and rk_gpio depend on their device options.

Reported by:	sbruno
2019-02-10 08:14:06 +00:00
Jayachandran C.
9088a4751c arm64 acpi: Add support for IORT table
Add new file arm64/acpica/acpi_iort.c to support the "IO Remapping
Table" (IORT). The table is specified in ARM document "ARM DEN 0049D"
titled "IO Remapping Table Platform Design Document".  The IORT table
has information on the associations between PCI root complexes, SMMU
blocks and GIC ITS blocks in the system.

The changes are to parse and save the information in the IORT table.
The API to use this information is added to sys/dev/acpica/acpivar.h.

The acpi_iort.c also has code to check the GIC ITS nodes seen in the
IORT table with corresponding entries in MADT table (for validity)
and with entries in SRAT table (for proximity information).

Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D18002
2019-02-07 02:30:33 +00:00
Emmanuel Vadot
2d5e81fbd0 mv_thermal: Add thermal driver for AP806 and CP110 thermal sensor
Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:33:05 +00:00
Emmanuel Vadot
44d027bb5d arm64: Add mv_cp110_icu and mv_cp110_gicp
icu is a interrupt concentrator in the CP110 block and gicp
is a gic extension to allow interrupts in the CP block to be turned
into GIC SPI interrupts

Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:08:43 +00:00
Emmanuel Vadot
2a3fb901a7 twsi: Clean up marvell part and add support for Marvell 7k/8k
Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:05:07 +00:00
Emmanuel Vadot
73450c4a7a arm64: marvell: Add cp110 clock controller support
The cp110 clock controller controls the clocks and gate of the CP110
hardware block.

Every clock/gate are implemented except the NAND clock.

Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:04:21 +00:00
Emmanuel Vadot
4f3a5b510b arm64: mv_gpio: Add Marvell 8K support
While here put the interrupts setup in it's own function

Sponsored by:	Rubicon Communications, LCC ("Netgate")
2018-12-12 22:02:57 +00:00
Emmanuel Vadot
e1453c9e4c arm64: marvell: Add driver for Marvell Ap806 System Controller
The first two clocks are for the clusters and their frequencies can be
found reading a register. Then a fixed 1200Mhz clock is present and two
fixed clocks, 'mss' which is 1200 / 6 and 'sdio' which is 1200 / 3.

Sponsored by:	Rubicon Communications, LLC ("Netgate")
2018-12-12 22:01:06 +00:00
Emmanuel Vadot
2d2a085222 arm64: mvebu_pinctrl: Add driver for Marvell Pinmux Controller
Add a driver compatible with Marvell mvebu-pinctrl and add ap806-pinctrl
support.

Sponsored by:	Rubicon Communications, LCC ("Netgate")
2018-12-12 22:00:05 +00:00
Emmanuel Vadot
277a038d0d arm64: allwinner: Add pwm driver
Add a pwm driver for Allwinner PWM
Add pwm and aw_pwm to the GENERIC kernel
2018-12-12 20:58:43 +00:00
Jayachandran C.
13aacaeea4 acpica: support parsing of arm64 affinity in acpi_pxm.c
ACPI SRAT table on arm64 uses GICC entries to provide CPU locality
information. These entries use an AcpiProcessorUid to identify the
CPU (unlike on x86 where the entries have an APIC ID).

Update acpi_pxm.c to extend the cpu_add/cpu_find/cpu_get_info
functions to handle AcpiProcessorUid. Use the updated functions
while parsing ACPI_SRAT_GICC_AFFINITY entry for arm64.

Also update sys/conf/files.arm64 to build acpi_pxm.c when ACPI is
enabled.

Reviewed by:	markj (previous version)
Differential Revision:	https://reviews.freebsd.org/D17942
2018-12-08 19:32:23 +00:00
Emmanuel Vadot
36ae7efe61 arm64/rockchip: add RK3399 support
Add CRU (Clock and Reset Unit) driver for RK3399.
Add support in rk_pinctrl driver.

Submitted by:  Greg V <greg@unrelenting.technology> (Original version)
Differential Revision: https://reviews.freebsd.org/D16732

MFC after:	1 month
2018-12-01 20:28:16 +00:00
Emmanuel Vadot
cee1927ea2 Add RK805 PMIC Support
RK805 is the companion PMIC for RK3328 SoC.
Add a driver for it with most of it's regulators supported.

MFC after:	1 month
2018-11-28 13:53:43 +00:00
Mateusz Guzik
a8e3f99ec1 amd64: implement memcmp in assembly
Both the in-kernel C variant and libc asm variant have very poor performance.
The former compiles to a single byte comparison loop, which breaks down even
for small sizes. The latter uses rep cmpsq/b which turn out to have very poor
throughput and are slower than a hand-coded 32-byte comparison loop.

Depending on size this is about 3-4 times faster than the current routines.

Reviewed by:	kib
Approved by:	re (gjb)
Differential Revision:	https://reviews.freebsd.org/D17328
2018-09-27 14:05:44 +00:00
Emmanuel Vadot
f9d40f5cca arm64: Make aw_sid and aw_thermal depend on nvmem
Both drivers use this interface so add a dependancy on it.
Since awg uses aw_sid for generating the MAC address, make it
depend on both aw_sid and nmvem so when only removing nvmem from
kernel config it will not include this driver.

Reported by:	sbruno
Approved by:	re (gjb)
2018-09-13 14:08:10 +00:00
Emmanuel Vadot
4ca213c07a a10_timer: Update the driver so we can use it on other SoC
a10_timer is currently use in UP allwinner SoC (A10 and A13).
Those don't have the generic arm timer.
The arm generic timecounter is broken in the A64 SoC, some attempts have
been made to fix the glitch but users still reported some minor ones.
Since the A64 (and all Allwinner SoC) still have this timer controller, rework
the driver so we can use it in any SoC.
Since it doesn't have the 64 bits counter on all SoC, use one of the
generic 32 bits counter as the timecounter source.

PR:	229644
2018-08-23 18:46:05 +00:00
Emmanuel Vadot
65aee3a872 arm64: allwinner: Add aw_syscon driver to GENERIC
Recent DTS use the syscon for the emac controller.
We support this but since U-Boot is still using old DTS it was never
needed for us to add this support, but this is a problem when using upstream
recent DTS and will be when U-Boot will catch up.

While here add a new compatible to the aw_syscon driver as Linux changed it ...
2018-08-19 18:55:33 +00:00
Luiz Otavio O Souza
6f207f5b47 Add support to the Marvell Xenon SDHCI controller.
Tested on Espresso.bin (37x0) and Macchiato.bin (8k) with SD cards and
eMMCs.

Obtained from:	pfSense
Sponsored by:	Rubicon Communications, LLC (Netgate)
2018-08-14 16:33:30 +00:00
Andrew Turner
a9dc38def4 Create an empty stdint.h for arm_neon.h to include.
The armv8crypto module includes arm_neon.h for the compiler intrinsic
functions. This includes the userland stdint.h file that doesn't exist in
the kernel. Fix this by providing an empty stdint.h to be used when we
include arm_neon.h.

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D16254
2018-07-16 15:39:33 +00:00
Marcin Wojtas
ab53b2929f Enable UART support for Xilinx Ultrascale+ SoCs
Xilinx Ultrascale+ are based on Cortex-A53 and use existing
UART driver (uart_dev_cdnc). Enable it in arm64 GENERIC config.

Submitted by: Michal Stanek <mst@semihalf.com>
Obtained from: Semihalf
2018-07-13 19:54:22 +00:00
Oleksandr Tymoshenko
9e28e9855f [rpi] Add SDHOST device driver for Raspberry Pi
SDHOST is another SD controller that is present on Raspberry Pi (the
other one is SDHC and handled by bcm2835_sdhci driver). Both
controllers are capable of providing interface to SD card, actual
configuration can be set in dtb file. At the moment custom DTBs for
RPi/RPi2 have sdhost node disabled. On RPi3 sdhost is disabled in
snapshot images by applying mmc.dtbo overlay. To enalbe both devices
user has to edit config.txt on FAT partition and remove or comment
"dtoverlay=mmc" line.

When no overlay applied on RPi3 SDHOST controls SD card and SDHC
interface can be used for SDIO. mmc.dtbo overlay disables SDHOST node
and switches SD card over to SDHC.  Likewise sdhost.dtbo overlay (not
currently included in snapshot image, but can be obtained from firmare
repo[1]) disabled SDHC node and switch SD card over to SDHOST.

[1] https://github.com/raspberrypi/firmware/tree/master/boot/overlays

Submitted by:	Klaus P. Ohrhallinger <k@7he.at>
Differential Revision:	https://reviews.freebsd.org/D14168
2018-06-28 21:14:33 +00:00
Ilya Bakulin
5e03278fee Add MMCCAM support to AllWinner MMC driver
Using MMCCAM on AllWinner boards is now possible, reaching highest
possible data transfer speed.

For now, MMCCAM doesn't scan cards on boot. This means that scanning
has to be done manually and that it's not possible to mount root FS
from MMC/SD card since there is no block device at the boot time.

For manually scanning the cards, run:
# camcontrol rescan X:0:0
Where X is the bus number (look at camcontrol devlist to determine
bus number assigned to the MMC controller).

Reviewed by:	manu
Approved by:	imp (mentor)
Differential Revision:	https://reviews.freebsd.org/D15891
2018-06-21 11:49:21 +00:00
Emmanuel Vadot
3de61a6883 rk_i2c: Add driver for the I2C controller present in RockChip SoC
This controller have a special mode for RX to help with smbus-like transfer
when the controller will automatically send the slave address, register address
and read the data. Use it when possible.
The same mode for TX is describe is the datasheet but is broken and have been
since ~10 years of presence of this controller in RockChip SoCs.

Attach this driver early at we need it to communicate with the PMIC early in the
boot.
Do not hook it to the kernel build for now.
2018-06-14 06:39:33 +00:00
Emmanuel Vadot
3476304a69 if_dwc_rk: Add DesignWare driver for RockChip SoCs.
Add driver for the designware ethernet controller found in some RockChip SoCs.
The driver still rely on a lot of things setup by the bootloader like clocks
and phy mode.
But since netbooting is the only/easiest way to boot rockchip board at the
moment add the driver so other people can test/dev on thoses boards.
2018-06-14 06:28:09 +00:00
Andrew Turner
f651b52527 Add support for the ARM SMC Calling Convention (SMCCC). This is a method
to call into the firmware in a similar way to the existing PSCI, and used
PSCI to detect when SMCCC is enabled.

There is a function ID space we can use. Currently we only support 3
functions in the ARM Architecture Calls region, however it is expected we
will expend these in the future.

Sponsored by:	DARPA, AFRL
2018-06-13 15:32:00 +00:00
Diane Bruce
5bede50958 Add a driver for the BCM2835 Mini-UART as seen on the RPi3
Reviewed by:	andrew
Approved by:	andrew
Differential Revision:	https://reviews.freebsd.org/D15684
2018-06-12 13:26:31 +00:00
Andrew Turner
619e50a657 Remove the psci option from arm64. It is now a standard option as it is
required to boot correctly.

Sponsored by:	DARPA, AFRL
2018-06-10 19:42:44 +00:00
Emmanuel Vadot
3df266dff9 arm64: rockchip: Add proper armclock support
The core clock (armclk) on RockChip SoC is special.
It can derive it's clock from many PLLs but RockChip recommand to do it
from "apll" on old SoC and "npll" on new SoC. The reason for choosing npll
is that it's have less jitter and is more close to the arm core on the SoC.
r333314 added the core clock as a composite clock but due to it's specials
property we need to deal with it differently.
A new rk_clk_armclk type is added for this and it supports only the "npll"
as we don't run on old RockChip SoC that only have the "apll".
It will always reparent to "npll" and set the frequency according to a rate
table that is known to be good.
For now we set the "npll" to the desired frequency and just set the core clk
divider to 1 as its parent it just used for the core clk.
2018-05-23 19:07:03 +00:00
Andrew Turner
79402150c1 Switch arm64 to use the same physmem code as 32-bit arm.
The main advantage of this is to allow us to exclude memory from being
used by the kernel. This may be from the memreserve property, or ranges
marked as no-map under the reserved-memory node.

More work is still needed to remove the physmap array. This is still used
for creating the DMAP region, however other patches need to be committed
before we can remove this.

Obtained from:	ABT Systems Ltd
Sponsored by:	Turing Robotic Industries
2018-05-22 11:07:04 +00:00
Emmanuel Vadot
3076898a56 allwinner: Add h3 spi driver
This driver is compatible with H3/H5/A64.
Test was done on the OrangePi-PC2 board (H5 based), which have a mx25l1606e
spi flash on it, by writing u-boot image, reading it and booting from the spi.
There is still room for improvement especially on reading using the controller
automatic burst which will avoid us to write dummy data to the TX FIFO.
DMA is also not supported as we currently don't support the DMA controller on
those SoCs
Only add a kernel module for it.
2018-05-17 10:19:52 +00:00
Emmanuel Vadot
cbf65cf228 arm64: rockchip: Add gpio controller driver
Add a driver that match on 'rockchip,gpio-bank', this compatible
string is found on almost all RockChip SoC so this driver is compatible
with almost all of the RockChip SoCs.

The only features missing for this driver are :
- Interrupts support
- Debouncing
2018-04-26 21:44:00 +00:00
Emmanuel Vadot
be2e72c286 arm64: rockchip: Add pinctrl driver
Add pinctrl driver for RockChip SoCs. This device manage which function
to set on which pin and some other properties like pull up/down, drive
strength etc ...
For now the driver only support RK3328 but it is versatile enough to
add support for other RockChip SoC in the future.
2018-04-26 21:37:38 +00:00
Emmanuel Vadot
49755fc6d2 arm64: rockchip: Add GRF driver
RockChip GRF (General Register Files) is present on almost all RockChip
SoC and is used to control some area of the system like iomuxing, gpio
or usb phy.
We need it to be probed and attached early in the boot process so
subclass syscon_generic and set the pass to BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE.
2018-04-26 21:35:04 +00:00
Ruslan Bukin
5819c3eb8a Enable Qualcomm Debug Subsystem (QDSS) block on MSM8916 SoC.
This is required for ARM Coresight operation on Dragonboard 410c.

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D14987
2018-04-10 12:53:48 +00:00
Ruslan Bukin
b09de0b34a Add support for the Coresight technology from ARM Ltd.
ARM Coresight is a solution for debug and trace of complex SoC designs.

This includes a collection of drivers for ARM Coresight interconnect
devices within a small Coresight framework.

Supported devices are:
o Embedded Trace Macrocell v4 (ETMv4)
o Funnel
o Dynamic Replicator
o Trace Memory Controller (TMC)
o CPU debug module

Devices are connected to each other internally in SoC and the
configuration of each device endpoints is described in FDT.

Typical trace flow (as found on Qualcomm Snapdragon 410e):
CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM
CPU1 -> ETM1 -^
CPU2 -> ETM2 -^
CPU3 -> ETM3 -^

Note that both Embedded Trace FIFO (ETF) and Embedded Trace Router (ETR)
are hardware configurations of TMC.

This is required for upcoming HWPMC tracing support.

This is tested on single-core system only.

Reviewed by:	andrew (partially)
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D14618
2018-04-05 15:45:54 +00:00
Andrew Turner
08fdb4ce38 Add an acpi attachment to the pci_host_generic driver and have the ACPI
bus provide it with its needed memory resources.

This allows us to use PCIe on the ThunderX2 and, with a previous version
of the patch, on the SoftIron 3000 with ACPI.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
Sponsored by:	DARPA, AFRL
Sponsored by:	Cavium (Hardware)
Differential Revision:	https://reviews.freebsd.org/D8767
2018-03-07 10:47:27 +00:00
Emmanuel Vadot
a5091e03c5 dwmmc_rockchip: Add support for rk3328-dw-mshc
* Do not use pio mode like rk2928
* Change clocks frequency in update_ios

Tested-On:    Pine64 Rock64 (RK3328)
2018-02-26 21:29:01 +00:00
Emmanuel Vadot
2a3d5e3364 rk3328: Add support for this SoC
* rk_cru is a cru driver that needs to be subclassed by
  the real CRU driver
* rk_clk_pll handle the pll type clock on RockChip SoC, it's only read
  only for now.
* rk_clk_composite handle the different composite clock types (with gate,
  with mux etc ...)
* rk_clk_gate handle the RockChip gates
* rk_clk_mux handle the RockChip muxes (unused for now)
* Only clocks for supported devices are supported for now, the rest will be
  added when driver support comes
* The assigned-clock* property are not handled for now so we rely a lot on the
  bootloader to setup some initial values for some clocks.
2018-02-26 21:25:50 +00:00
Andrew Turner
ee42eb7e5c iAdd ACPI attachments the the GIC and GICv3 interrupt controller drivers.
For each we need to walk the MADT to find which we have, then add the
driver as needed. As each may have a child they will each walk the same
table to find these details.

Reviewed by:	mmel
Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D8720
2018-01-11 17:23:24 +00:00
Andrew Turner
224c3776f6 Add the start of INTRNG support for ACPI.
This adds a new acpi_bus interface with a map_intr method. This is similar
to the Open Firmware map_intr method and allows us to create the needed
mapping from ACPI space to INTRNG space.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D8617
2018-01-11 17:09:12 +00:00
Andrew Turner
4bb409fb8d Add a framework to install CPU errata on arm64. Each erratum can encode
a mask and value to compare with the Main ID Register. If these match then a
function is called to handle the installation of the erratum workaround.

No errata are currently handled, however this will change soon in a future
commit.

MFC after:	1 week
Sponsored by:	DARPA, AFRL
2018-01-09 14:33:05 +00:00
Emmanuel Vadot
98b306dcfd arm64: Remove old clock driver for Allwinner 64bit SoC
All the clocks are now handled by the clkng driver.

Tested On: Pine64-LTS (A64)
Tested On: OrangePi PC2 (H5)
2018-01-06 20:32:14 +00:00
Kyle Evans
2defb358ea if_awg: Use syscon prop if it exists
The emac bindings that are landing in Linux 4.15 specify a syscon property
on the emac node that point to /soc/syscon. Use this property if it's
specified, but maintain backwards compatibility with the old method.

The older method is still used for boards that we get .dtb from u-boot, such
as pine64, that did not yet have stable emac bindings.

Tested on:	Banana Pi-M3 (a83t)
Tested on:	Pine64 (a64)
Reviewed by:	manu
Differential Revision:	https://reviews.freebsd.org/D13296
2018-01-04 22:37:15 +00:00
Emmanuel Vadot
99de54f18a arm64: a10_gpio.c and a10_mmc.c were renamed aw_gpio.c and aw_mmc.c 2017-12-26 15:35:19 +00:00
Emmanuel Vadot
34b8ef3d77 Allwinner H5: Enhance support
Add proper gpio and clock support
2017-12-05 21:21:23 +00:00
Ed Schouten
aea6d042a9 Port cloudabi32.ko to FreeBSD/arm64.
This change adds an implementation of a sysent for running CloudABI
armv6 and armv7 binaries on FreeBSD/arm64. It is a somewhat literal copy
of the armv6 version, except that it's been patched up to use the proper
registers.

Just like for cloudabi32.ko on FreeBSD/amd64, we make use of a vDSO that
automatically pads system call parameters to 64-bit value. These are
stored in a buffer on the stack, meaning we need to use copyin() and
copyout() unconditionally.
2017-11-30 17:58:48 +00:00
Ed Schouten
9dcf90f8ad Add rudimentary support for building FreeBSD/arm64 with COMPAT_FREEBSD32.
Right now I'm using two Raspberry Pi's (2 and 3) to test CloudABI
support for armv6, armv7 and aarch64. It would be nice if I could
restrict this to just a single instance when testing smaller changes.
This is why I'd like to get COMPAT_CLOUDABI32 to work on arm64.

As COMPAT_CLOUDABI32 depends on COMPAT_FREEBSD32, at least for the ELF
loading, this change adds all of the bits necessary to at least build a
kernel with COMPAT_FREEBSD32. All of the machine dependent system calls
are still stubbed out, for the reason that implementations for these are
only useful if actual support for running FreeBSD binaries is added.
This is outside the scope of this work.

Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D13144
2017-11-24 13:50:53 +00:00