7 Commits

Author	SHA1	Message	Date
brooks	9a1a8ad690	MFP4: ... Change 227630 by bz@bz_zenith on 2013/04/12 08:50:27 Implement soft reset setting sr in sr and just in case loop endlessly afterwards. MFC after: 3 days Sponsored by: DARPA/AFRL	2013-10-18 15:40:37 +00:00
attilio	cb47f0509b	Merge from vmobj-rwlock branch: ... Remove unused inclusion of vm/vm_pager.h and vm/vnode_pager.h. Sponsored by: EMC / Isilon storage division Tested by: pho Reviewed by: alc	2013-02-26 01:00:11 +00:00
rwatson	9a5b2389dd	Merge Perforce change @219948 to head: ... Add code so that the BERI boot process can ask the kernel linker for DTB blobs that may have been left for it by the boot loader, as done on PowerPC and ARM. This will require both a more mature boot loader, and more mature boot loader argument passing mechanism, than currently supported on BERI. Sponsored by: DARPA, AFRL	2013-01-12 13:20:21 +00:00
rwatson	fe7ea72483	Merge Perforce change @219935 to head: ... Initialise Openfirmware/FDT code earlier in the FreeBSD/beri boot, so that the results will be available for configuring the console UART (eventually). Suggested by: thompsa Sponsored by: DARPA, AFRL	2013-01-12 12:34:59 +00:00
rwatson	96cc82a0b4	Merge @219932 from Perforce: ... FDT headers can't be included if the kernel is compiled without FDT support, due to dependence on generated kobj headers. BERI supports both FDT and non-FDT kernels. Spotted by: bz	2013-01-01 19:42:06 +00:00
rwatson	c285310a0b	If FDT is compiled into a FreeBSD/beri kernel, initialise OpenFirmware. ... Sponsored by: DARPA, AFRL	2012-12-31 11:06:37 +00:00
rwatson	bf6955f98a	Add preliminary support for the SRI International / University of Cambridge ... Bluespec Extensible RISC Implementation (BERI) processor. BERI is a 64-bit MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs, and is being used for CPU and OS research at several institutions. Sponsored by: DARPA, AFRL	2012-08-25 08:31:21 +00:00