Commit Graph

13 Commits

Author SHA1 Message Date
pfg
4736ccfd9c sys: further adoption of SPDX licensing ID tags.
Mainly focus on files that use BSD 3-Clause license.

The Software Package Data Exchange (SPDX) group provides a specification
to make it easier for automated tools to detect and summarize well known
opensource licenses. We are gradually adopting the specification, noting
that the tags are considered only advisory and do not, in any way,
superceed or replace the license texts.

Special thanks to Wind River for providing access to "The Duke of
Highlander" tool: an older (2014) run over FreeBSD tree was useful as a
starting point.
2017-11-20 19:43:44 +00:00
jhibbits
801b632ef5 Set EN_MAS7_UPDATE HID0 bit for e500 core.
Without enabling this bit, tlbre and tlbsx don't update the MAS7 register,
resulting in garbage in the register after a read (rather, the previous setting
of it for a tlbwe).  This can result in mmu_booke_mapdev_attr() thinking
mappings that should match actually don't, because tlb1_read_entry() can't
determine the correct address of a given entry.

MFC after:	11-RELEASE
2016-08-07 19:09:56 +00:00
raj
c4e990d23d Update HID defines for E500mc and E5500 CPU cores.
Obtained from:	Freescale, Semihalf
2012-05-25 21:12:24 +00:00
nwhitehorn
2127edd2e4 MFppc64:
Kernel sources for 64-bit PowerPC, along with build-system changes to keep
32-bit kernels compiling (build system changes for 64-bit kernels are
coming later). Existing 32-bit PowerPC kernel configurations must be
updated after this change to specify their architecture.
2010-07-13 05:32:19 +00:00
nwhitehorn
4a8797cf0c Turn on NAP mode on G5 systems, and refactor the HID0 setup code a little.
This makes my G5 Xserve sound slightly less like it is filled with
howling banshees.
2009-10-24 18:33:01 +00:00
raj
8f223712eb Centralize setting HID0/1 for E500. Rename HID defines which are specific
to E500 rather than shared within Book-E family.

Obtained from:	Freescale, Semihalf
2009-04-22 13:11:38 +00:00
nwhitehorn
32d233ecc5 Rework the way we get the cacheline size. Instead of having a table of
CPUs known to use 128 byte cache lines and defaulting to 32, use the dcbz
instruction to measure it. Also make dcbz behave the way you would
expect on PPC 970.
2009-04-12 03:03:55 +00:00
nwhitehorn
ef1e56b6d4 Add support for 64-bit PowerPC CPUs operating in the 64-bit bridge mode
provided, for example, on the PowerPC 970 (G5), as well as on related CPUs
like the POWER3 and POWER4.

This also adds support for various built-in hardware found on Apple G5
hardware (e.g. the IBM CPC925 northbridge).

Reviewed by:    grehan
2009-04-04 00:22:44 +00:00
raj
3dea77f93c Unify and generalize PowerPC headers, adjust AIM code accordingly.
Rework of this area is a pre-requirement for importing e500 support (and
other PowerPC core variations in the future). Mainly the following
headers are refactored so that we can cover for low-level differences between
various machines within PowerPC architecture:

  <machine/pcpu.h>
  <machine/pcb.h>
  <machine/kdb.h>
  <machine/hid.h>
  <machine/frame.h>

Areas which use the above are adjusted and cleaned up.

Credits for this rework go to marcel@

Approved by:	cognet (mentor)
MFp4:		e500
2008-03-02 17:05:57 +00:00
raj
ec4d22c527 Teach PowerPC CPU identification routines to recognize e500 cores. Fix style
issues in this area.

Approved by:	cognet (mentor)
MFp4:		e500
2008-02-25 00:09:23 +00:00
grehan
e896fb7aff HID0 updates:
- updated relevant models for High BAT enable bit
 - fixed bug in BHTCLR/XAEN constants
 - added LRSTK and FOLD bits
2005-02-04 01:14:38 +00:00
grehan
9d3fe37acc Definitions for MPC7457 CPU type and HID0 bits 2004-02-09 00:12:50 +00:00
benno
33c2dbc662 - Update spr.h
- Add hid.h

Obtained from:	NetBSD

NOTE: This undoes some changes I'd made to prefix the processor name defines
with PVR_.  This was due to my original decision to use MPC750 as a cpu name.
With this changed, the PVR_ change is no longer required.
2003-02-05 12:04:29 +00:00