Commit Graph

480 Commits

Author SHA1 Message Date
jhb
9d0e5620ec Blacklist a few more Intel chipsets re: MSI based on user reports:
E7500 and 855.
2007-01-12 21:30:25 +00:00
jhb
80c43bc68b - Condense the comment for Intel chipset MSI blacklist entries.
- Blacklist the E7210.

PR:		kern/105768 (2)
Reported by:	marcus (2)
2007-01-12 13:33:56 +00:00
jhb
9983d83070 Disable MSI on the Intel E7505 chipset. It is reported broken on a Tyan
S2665ANF motherboard.

Reported by:	"Eugene M. Kim" <blue at white lv>
2006-12-28 06:14:42 +00:00
jhb
afc4eef817 Disable MSI for the Intel E7501 chipset.
Reported by:	jdp
2006-12-14 19:59:29 +00:00
jhb
a33da981f5 Add a first pass at a way to blacklist MSI on systems where it doesn't
work:
- A new PCI quirk (PCI_QUIRK_DISABLE_MSI) is added to the quirk table.
- A new pci_msi_device_blacklisted() determines if a passed in device
  matches an MSI quirk in the quirk table.  This can be overridden (all
  quirks ignored) by setting the hw.pci.honor_msi_blacklist to 0.
- A global blacklist check is performed in the MI PCI bus code by checking
  to see if the device at 0:0:0 is blacklisted.

Tested by:	jdp
2006-12-14 19:57:06 +00:00
jhb
ed2852300f Replace #define<space> with #define<tab> so the code is consistent with
style(9) and avoids mixing the two formats.
2006-12-14 16:53:48 +00:00
jhb
c1afd80576 - Add constants for HT PCI capability registers including the various
subtypes of HT capabilities.
- Add constants for the MSI mapping window HT PCI capability.
- On i386 and amd64, enable the MSI mapping window on any HT bridges we
  encounter and report any non-standard mapping window addresses.
2006-12-12 19:33:25 +00:00
jhb
1449922d2d Give the WREG() macro the same lifetime as the REG() macro. 2006-12-12 19:30:40 +00:00
jhb
b3bf7cec94 Add some bootverbose printf's to detail how many MSI messages are allocated
and to which IRQs.

Requested by:	scottl
2006-12-12 19:29:01 +00:00
jmg
97ee785c18 don't mark the cksum as invalid here... off is incorrect when we get
here, it's either unset, or it's valid, so we don't need to do anything
different...

Reported by:	Neterion (via rwatson)
2006-11-21 05:46:09 +00:00
jhb
3b565e6dd2 Look for capabilities in PCI-PCI bridges using the same CAP PTR register
as for type 0 devices.

Submitted by:	grehan
MFC after:	1 week
2006-11-16 17:31:33 +00:00
jhb
44878f2858 Fix a couple of comment typos.
Reported by:	ru
2006-11-14 17:54:55 +00:00
jhb
d055bdf0ca First cut at MI support for PCI Message Signalled Interrupts (MSI):
- Add 3 new functions to the pci_if interface along with suitable wrappers
  to provide the device driver visible API:
  - pci_alloc_msi(dev, int *count) backed by PCI_ALLOC_MSI().  '*count'
    here is an in and out parameter.  The driver stores the desired number
    of messages in '*count' before calling the function.  On success,
    '*count' holds the number of messages allocated to the device.  Also on
    success, the driver can access the messages as SYS_RES_IRQ resources
    starting at rid 1.  Note that the legacy INTx interrupt resource will
    not be available when using MSI.  Note that this function will allocate
    either MSI or MSI-X messages depending on the devices capabilities and
    the 'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables.  Also note
    that the driver should activate the memory resource that holds the
    MSI-X table and pending bit array (PBA) before calling this function
    if the device supports MSI-X.
  - pci_release_msi(dev) backed by PCI_RELEASE_MSI().  This function
    releases the messages allocated for this device.  All of the
    SYS_RES_IRQ resources need to be released for this function to succeed.
  - pci_msi_count(dev) backed by PCI_MSI_COUNT().  This function returns
    the maximum number of MSI or MSI-X messages supported by this device.
    MSI-X is preferred if present, but this function will honor the
    'hw.pci.enable_msix' and 'hw.pci.enable_msi' tunables.  This function
    should return the largest value that pci_alloc_msi() can return
    (assuming the MD code is able to allocate sufficient backing resources
    for all of the messages).
- Add default implementations for these 3 methods to the pci_driver generic
  PCI bus driver.  (The various other PCI bus drivers such as for ACPI and
  OFW will inherit these default implementations.)  This default
  implementation depends on 4 new pcib_if methods that bubble up through
  the PCI bridges to the MD code to allocate IRQ values and perform any
  needed MD setup code needed:
  - PCIB_ALLOC_MSI() attempts to allocate a group of MSI messages.
  - PCIB_RELEASE_MSI() releases a group of MSI messages.
  - PCIB_ALLOC_MSIX() attempts to allocate a single MSI-X message.
  - PCIB_RELEASE_MSIX() releases a single MSI-X message.
- Add default implementations for these 4 methods that just pass the
  request up to the parent bus's parent bridge driver and use the
  default implementation in the various MI PCI bridge drivers.
- Add MI functions for use by MD code when managing MSI and MSI-X
  interrupts:
  - pci_enable_msi(dev, address, data) programs the MSI capability address
    and data registers for a group of MSI messages
  - pci_enable_msix(dev, index, address, data) initializes a single MSI-X
    message in the MSI-X table
  - pci_mask_msix(dev, index) masks a single MSI-X message
  - pci_unmask_msix(dev, index) unmasks a single MSI-X message
  - pci_pending_msix(dev, index) returns true if the specified MSI-X
    message is currently pending
- Save the MSI capability address and data registers in the pci_cfgreg
  block in a PCI devices ivars and restore the values when a device is
  resumed.  Note that the MSI-X table is not currently restored during
  resume.
- Add constants for MSI-X register offsets and fields.
- Record interesting data about any MSI-X capability blocks we come
  across in the pci_cfgreg block in the ivars for PCI devices.

Tested on:	em (i386, MSI), bce (amd64/i386, MSI), mpt (amd64, MSI-X)
Reviewed by:	scottl, grehan, jfv
MFC after:	2 months
2006-11-13 21:47:30 +00:00
jmg
1a66ce5fa5 fix hanging on invalid data... (This doesn't fix hanging due to broken
hardware)...

Tested by:	Ian Dowse, Adam K Kirchhoff and Vladimir Kushnir
2006-11-09 21:05:32 +00:00
jhb
417d61baef Don't try to print a NULL string during boot. If a device doesn't have a
valid name yet, just omit the name during the bootverbose printfs.

MFC after:	1 week
2006-11-09 18:04:53 +00:00
jhb
f1be25c7ac Various whitespace cleanups. 2006-11-07 18:55:51 +00:00
imp
c3cb71bca5 Doh! Actually commit checking against NULL for res.
Noticed by: dougb@
2006-11-04 06:56:51 +00:00
imp
82791e6dba Assign start to the value we were able to allocate and use that to
write out the BAR.  Otherwise, we were trying to shift a 32-bit
quantity on 32-bit platforms.  Also, 'start' check sanity to where it
is known.
2006-10-30 22:46:33 +00:00
imp
4bea281f9a More fully support 64-bit bars. Prior to this commit, we supported
only those bars that had addresses assigned by the BIOS and where the
bridges were properly programmed.  Now even unprogrammed ones work.
This was needed for sun4v.  We still only implement up to 2GB memory
ranges, even for 64-bit bars.  PCI standards at least through 2.2 say
that this is the max (or 1GB is, I only know it is < 32bits).

o Always define pci_addr_t as uint64_t.  A pci address is always 64-bits,
  but some hosts can't address all of them.
o Preserve the upper half of the 64-bit word during resource probing.
o Test to make sure that 64-bit values can fit in a u_long (true on some
  platforms, but not others).  Don't use those that can't.
o minor pedantry about data sizes.
o Better bridge resource reporting in bootverbose case.
o Minor formatting changes to cope with different data types on different
  platforms.

Submitted by: jmg, with many changes by me to fully support 64-bit
addresses.
2006-10-30 19:18:46 +00:00
jmg
c113c03770 fix tab indentation for CP and RV...
If the length is zero, catch this early, instead of making dflen go negative
and letting bad things happen...  We also check to see if RV (checksum) is
0, and handle that has a checksum failure...

Properly handle checksum failures by not processing read-write VPD data,
and removing all the found read-only data...

Tested by:	oleg (dflen going negative)
2006-10-20 21:28:11 +00:00
imp
a44c175cd0 Remove redundant casts. The casts inside the macros should be
sufficient (or fixed if not).
2006-10-12 03:05:45 +00:00
jmg
6a8dfa7618 provide routines to access VPD data at the PCI layer...
remove sk's own implementation, and use the new calls to get the data...

Reviewed by:	-arch
2006-10-09 16:15:56 +00:00
ru
c29a0764f4 Actually make bounds checking for PCIOCREAD and PCIOCWRITE work. 2006-10-06 14:31:32 +00:00
jmg
f09ac5a545 spell PCIS_CRYPTO_ENTERTAIN properly...
MFC after:	3 days
2006-09-20 06:47:14 +00:00
yar
209e4786e7 Commit the results of the typo hunt by Darren Pilgrim.
This change affects documentation and comments only,
no real code involved.

PR:		misc/101245
Submitted by:	Darren Pilgrim <darren pilgrim bitfreak org>
Tested by:	md5(1)
MFC after:	1 week
2006-08-04 07:56:35 +00:00
jhb
a72b0bcd7f Simplify the pager support in DDB. Allowing different db commands to
install custom pager functions didn't actually happen in practice (they
all just used the simple pager and passed in a local quit pointer).  So,
just hardcode the simple pager as the only pager and make it set a global
db_pager_quit flag that db commands can check when the user hits 'q' (or a
suitable variant) at the pager prompt.  Also, now that it's easy to do so,
enable paging by default for all ddb commands.  Any command that wishes to
honor the quit flag can do so by checking db_pager_quit.  Note that the
pager can also be effectively disabled by setting $lines to 0.

Other fixes:
- 'show idt' on i386 and pc98 now actually checks the quit flag and
  terminates early.
- 'show intr' now actually checks the quit flag and terminates early.
2006-07-12 21:22:44 +00:00
imp
eea2675a24 Add a define for the Standard SD Host Controller Base Peripheral. 2006-05-30 21:36:12 +00:00
jhb
3627ded047 Workaround a hang on some nForce2 systems that can happen if the CPU goes
into and out of the halt state very quickly.

Submitted by:	Andriy Gapon <avg at icyb dot net dot ua>
MFC after:	1 week
2006-05-24 14:08:31 +00:00
jhb
215bc87cc3 Fixup some comments to allow for the fact that PCI domains are not specific
to Alpha hoses.
2006-05-11 22:13:21 +00:00
marcel
3f80cf7f43 The size of I/O ranges can be anything from 16 bytes to 2G bytes.
Lower the minimum for memory mapped I/O from 32 bytes to 16 bytes.
This fixes bus enumeration on ia64 now that the Diva auxiliary
serial port is attached to.
2006-04-27 04:53:18 +00:00
jkim
782918fd85 Free allocated environment variables after use.
Coverity ID:	366
Found by:	Coverity Prevent
2006-04-21 19:35:03 +00:00
jhb
16c9ed73d6 Don't add an agp child in vgapci's attach routine if the PCIY_AGP
capability is present as not all devices supported by the agp_i810 driver
(such as i915) have the AGP capability.  Instead, add an identify routine
to the agp_i810 driver that uses the PCI ID to determine if it should
create an agp child device.
2006-02-01 15:45:29 +00:00
jhb
811fcee48a Make the 'pci_devclass' pointer variable private (drivers really shouldn't
share devclass pointers, a mistake I've encouraged in the past) and
move the declaration of the pci_driver kobj class from cardbus.c to
pci_private.h so that other drivers can inherit from pci_driver.
2006-01-20 22:00:50 +00:00
jhb
170b22254d - Make pcib_devclass private to sys/dev/pci/pci_pci.c and change all the
various pcib drivers to use their own private devclass_t variables for
  their modules.
- Use the DEFINE_CLASS_0() macro to declare drivers for the various pcib
  drivers while I'm here.
2006-01-06 19:22:19 +00:00
imp
6643030861 Use __HAVE_ACPI and __PCI_REROUTE_INTERRUPT as appropriate rather than
the complicated #ifdefs.
2006-01-01 21:04:31 +00:00
imp
12d4e274cb Remove left-over #ifdef alpha routines. They aren't used by any of
our drivers, and don't appear to be necessary for GENERIC and LINT on
the alpha.  They don't belong in a MI header anyway...
2006-01-01 20:40:08 +00:00
imp
d3a57d50d3 Remove stray debug from p4 integration. 2006-01-01 08:26:39 +00:00
imp
737f13e6f5 Make RID2BAR actually return a number that can be plugged into PCIR_BAR()
rather than a bitmask.

Submitted by: ru@
2005-12-30 20:25:40 +00:00
imp
6e8e63097f Remove debug now that I've looped back the big changes into my p4 tree. 2005-12-30 19:36:29 +00:00
imp
8b10395635 Expose pci_add_resources to the outside world, add a 'force' flag to
force allocation of unallocated BARs (cardbus uses this to preallocate
everything).  Add a prefetchmask to allow for busses that get prefetch
hints to set them.  Addjust pci_add_map and pci_ata_maps to take a new
force flag which pci_add_resources will pass in.  Implement 'force' in
pci_add_map.  Write new value of allocated resource into the bar, if
the allocation succeeded (we should have done this before, but with
the new force the bug was very obvious).
2005-12-30 19:28:26 +00:00
imp
e57b04f29b Add a macro to map from BAR to rid # (inverse of PCIR_BARS). 2005-12-29 23:40:41 +00:00
jhb
d4cd89f6af Return BUS_PROBE_GENERIC rather than 0 in the probe routine.
Requested by:	marius
2005-12-22 16:25:22 +00:00
jhb
bf7979fcfe Add a vgapci(4) stub device driver for VGA PCI devices. This device serves
as a bus so that other drivers such as drm(4), acpi_video(4), and agp(4)
can attach to it thus allowing multiple drivers for the same device.  It
also removes the need for the drmsub hack for the i8[13]0/i915 drm and agp
drivers.
2005-12-20 22:41:33 +00:00
jhb
fde66b5a2e Move the hostb driver out of the i386 and amd64 PCI code (where it was
duplicated anyways) and into a single MI driver.  Extend the driver a bit
to implement the bus and PCI kobj interfaces such that other drivers can
attach to it and transparently act as if their parent device is the PCI
bus (for the most part).
2005-12-20 21:09:45 +00:00
jhb
54f0fa09ad Add a new method PCI_FIND_EXTCAP() to the pci bus interface that is used
to search for a specific extended capability.  If the specified capability
is found for the given device, then the function returns success and
optionally returns the offset of that capability.  If the capability is
not found, the function returns an error.
2005-12-20 19:57:47 +00:00
imp
15d22053de Improve diagnostic message. 2005-11-09 03:37:52 +00:00
imp
a8ba39ce7d MFp4: When doing lazy allocation, it turns out that we need to record the
actual resource values we received from the system rather than the range
we requested.  Since we request a range starting at 0, we would record
that number.  Later, since this == 0, we'd allocate again.  However,
we wouldn't write the new resource into the BAR.  This resulted in
a resource leak as well as a BAR that couldn't access the resource at
all since rman_get_start, et al, were wrong.

MFC After: 1 week (assuming RELENG_6 is open for business)
2005-10-29 05:52:17 +00:00
imp
e1cda542a5 Use symbolic name rather thanhard coding the cap pointer offset for
type two devices.
2005-10-29 05:49:06 +00:00
imp
eea6bf62c7 Add PCIM_BIOS_ADDR_MASK too 2005-10-28 06:02:51 +00:00
imp
397e6b5e42 Some cardbus CIS definitions moved here since they are PCI registers. 2005-10-28 05:57:10 +00:00