rather than inlines. These are compiled with -fomit-frame-pointer and
work out pretty close to the original routines, but it might be a fraction
slower. The reason for doing this is to prevent the SWI_* and HWI_* values
from being compiled into drivers and lkms etc which is one of the things
that prevents the same lkm from being used on both SMP and UP kernels.
This gives us a lot more scope for experimenting with the splxxx
implementaton for SMP parallelism etc.
Reviewed by: bde
CPU code-named `M2'.
- Use the result of cpuid instruction instead of DIR to identify
6x86MX cpu. DIR0 and DIR1 are not documented in the data sheet, and
cpuid instruction is enabled at reset time.
- Add a function, init_6x86MX() to initialize 6x86MX cpu. It supports
CPU_SUSP_HLT and CPU_IORT options. It always sets NC1 (640K - 1M is
not cached.), and enables L1 cache in write-back mode.
- Fix typo in the comment in identblue().
Hopefully I've done the proper magic to merge changes between 1.17 and
1.17.2.1 into the main trunk. Description of those changes follows:
Brought in changes sent to me in late 1995 by Rich Murphey.
I cleaned up a few things and am currently running these under
2.2-970205-GAMMA.
The changes deal with software debouncing apparently necessary on
todays faster hardware, and also some problems with the use of the -Select
line for the TW-523 sync. This driver allows use of +PaperEnd as an
alternative.
Changes to pmap.c for lapic_t lapic && ioapic_t ioapic pointers,
currently equal to apic_base && io_apic_base, will stand alone with the
private page mapping.
apic.h has defines like:
#define lapic__id lapic->id
Once private pages and "known virtual addr" mapping of the APICs is
ready all 'lapic__XXX' will be changed to 'lapic.XXX', and the defines
will be removed.
Changes to smp.h for lapic_t lapic && ioapic_t ioapic pointers,
currently equal to apic_base && io_apic_base, will stand alone with the
private page mapping.
Return failure, if the enable bit corresponding to the map type has not
been set in the command register. This feature was requested by Justin
Gibbs, who pointed out that some early PCI to PCI bridges do not correctly
support memory windows (I assume because of the risk of deadlocks that
have been taken care of in the PCI 2.2 spec) and that some BIOS clears
the memory address decode enable bit in the command register of the PCI
device, if it finds them behind such a bridge.
1) Stop at the first map register that contains a zero value.
2) When testing for the map size work up from low values, since
this works around a bug in some BusLogic SCSI card, which has
the 16 upper port base address bits hardwired to zero.
The config register dump printed in the bootverbose case has
been slightly rearranged.
Adjust the data port address by adding the two low order bits of
the register number. The address port takes only a word address
(i.e. ignores the two low order bits written to it).
