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6 Commits

Author SHA1 Message Date
Sean Bruno
4b226201da Trailing whitespace cleanup along with 80 column enforcemnt. 
Submitted by:	hiren.panchasara@gmail.com
Reviewed by:	sbruno@freebsd.org
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
 2013-04-03 21:34:35 +00:00
Sean Bruno
cc0c1555d3 Update hwpmc to support Haswell class processors. 
0x3C:      /* Per Intel document 325462-045US 01/2013. */

Add manpage to document all the goodness that is available in this
processor model.

Submitted by:	hiren panchasara <hiren.panchasara@gmail.com>
Reviewed by:	jimharris, sbruno
Obtained from:	Yahoo! Inc.
MFC after:	2 weeks
 2013-03-28 19:15:54 +00:00
Davide Italiano
78d763a29b - Add support for the Intel Sandy Bridge microarchitecture (both core and uncore counting events) 
- New manpages with event lists.
- Add MSRs for the Intel Sandy Bridge microarchitecture

Reviewed by:	attilio, brueffer, fabient
Approved by:	gnn (mentor)
MFC after:	3 weeks
 2012-03-01 21:23:26 +00:00
George V. Neville-Neil
ad71f089ab Clean up a switch statement for uncore events on Westmere processors. 
Submitted by:	Davide Italiano
Reviewed by:	gnn
MFC after:	1 week
 2012-01-13 17:13:46 +00:00
Fabien Thomas
3444c31af6 Add missing MSR programming for some events. 
Submitted by:	Davide Italiano <davide.italiano@gmail.com>
MFC after:	3 days
 2012-01-04 07:33:06 +00:00
Fabien Thomas
1fa7f10bac - Support for uncore counting events: one fixed PMC with the uncore 
domain clock, 8 programmable PMC.
- Westmere based CPU (Xeon 5600, Corei7 980X) support.
- New man pages with events list for core and uncore.
- Updated Corei7 events with Intel 253669-033US December 2009 doc.
  There is some removed events in the documentation, they have been
  kept in the code but documented in the man page as obsolete.
- Offcore response events can be setup with rsp token.

Sponsored by: NETASQ
 2010-04-02 13:23:49 +00:00