15 Commits

Author SHA1 Message Date
mmel
4b670ed804 Fix cut&paste typo in atomic_fetchadd_64().
Reported by:	Jia-Shiun Li <jiashiun@gmail.com>
MFC after:	1 week
2018-12-07 11:10:27 +00:00
jhb
07f4bcbf2f Fix some harmless type mismatches in the ARM atomic_cmpset implementations.
The return value of atomic_cmpset() and atomic_fcmpset() is an int (which
is really a bool) that has the values 0 or 1.  Some of the inlines were
using the type being operated on (e.g. uint32_t) as either the return type
of the function, or the type of a local 'ret' variable used to hold the
return value.  Fix all of these to just use plain 'int'.  Due to C promotion
rules and the fact that the value can only be 0 or 1, these should all be
harmless.

Reviewed by:	imp (only the v4 ones)
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D15147
2018-04-23 16:50:37 +00:00
cognet
4c8e8515c5 Correct the IT instruction in atomic_fcmpset_64().
Reported by:	andrew
2017-01-29 13:31:56 +00:00
cognet
3d8de9b140 Remove useless labels. 2017-01-28 17:48:33 +00:00
cognet
26d474bb03 Use strexeq instead of needlessly branch.
Suggested by:	ian
2017-01-28 17:46:04 +00:00
cognet
6a21064647 Implement atomic_fcmpset_* for arm and arm64. 2017-01-28 16:24:06 +00:00
mmel
b85d58737d ARM: Add mising early clobber modifier in atomic_swap_32().
MFC after: 2 weeks
2016-10-04 09:59:37 +00:00
mmel
f82aa438f9 ARM: Add atomic_swap_64(). It's need by linuxkpi and drm-next-4.7.
MFC after: 2 weeks
2016-10-04 09:51:54 +00:00
mmel
9a64fd96da ARM: Implement atomic_swap_int(9). It's used in DRM2 code.
Approved by:	kib (mentor)
2015-11-28 12:12:28 +00:00
kib
60024cd7aa Implement atomic_testandset_{32,int,long,64} for ARMv6. Only
little-endian configuration for 64-bit variant is supported.

Reviewed by:	mmel
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D4113
2015-11-10 12:15:13 +00:00
kib
a7abd83f35 FreeBSD does not support SMP on ARMv5. Since processor is always
self-consistent, there is no need in anything but compiler barrier in
the implementation of atomic_thread_fence_*() on ARMv5.  Split
implementation of fences for ARMv4/5 and ARMv6; the former use
compiler barriers, the later also perform hardware barriers.

An issue which is fixed by the change is the faults from the CP15
coprocessor accesses in the user mode.  This was uncovered by the
pthread_once() changes in r287556.

Reported by:	Mattia Rossi <mattia.rossi.mailinglists@gmail.com>
Discussed with:	alc, cognet, jhb
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
2015-10-02 13:21:08 +00:00
andrew
f281ef9050 Fix atomic_store_64, it should write the value passed in, not the value
read by the load.

Pointy Hat:	andrew
2015-07-19 16:55:47 +00:00
andrew
8672831bb4 Clean up the style of the armv6 atomic code.
Sponsored by:	ABT Systems Ltd
2015-07-19 15:44:51 +00:00
andrew
48cb0ec166 Sort the ARM atomic functions to be in alphabetical order.
Sponsored by:	ABT Systems Ltd
2015-07-19 13:10:47 +00:00
andrew
6832ce6374 Split out the arm and armv6 parts of atomic.h to new files. While here use
__ARM_ARCH to determine which revision of the architecture is applicable.

Sponsored by:	ABT Systems Ltd
2015-07-16 13:33:03 +00:00