Commit Graph

16 Commits

Author SHA1 Message Date
marius
b4610d98b0 - Import the common MII bitbang'ing code from NetBSD and convert drivers to
take advantage of it instead of duplicating it. This reduces the size of
  the i386 GENERIC kernel by about 4k. The only potential in-tree user left
  unconverted is xe(4), which generally should be changed to use miibus(4)
  instead of implementing PHY handling on its own, as otherwise it makes not
  much sense to add a dependency on miibus(4)/mii_bitbang(4) to xe(4) just
  for the MII bitbang'ing code. The common MII bitbang'ing code also is
  useful in the embedded space for using GPIO pins to implement MII access.
- Based on lessons learnt with dc(4) (see r185750), add bus barriers to the
  MII bitbang read and write functions of the other drivers converted in
  order to ensure the intended ordering. Given that register access via an
  index register as well as register bank/window switching is subject to the
  same problem, also add bus barriers to the respective functions of smc(4),
  tl(4) and xl(4).
- Sprinkle some const.

Thanks to the following testers:
Andrew Bliznak (nge(4)), nwhitehorn@ (bm(4)), yongari@ (sis(4) and ste(4))
Thanks to Hans-Joerg Sirtl for supplying hardware to test stge(4).

Reviewed by:	yongari (subset of drivers)
Obtained from:	NetBSD (partially)
2011-11-01 16:13:59 +00:00
yongari
05362e1a1e Implement RX interrupt moderation using one-shot timer interrupt.
Unlike TX interrupt, ST201 does not provide any mechanism to
suppress RX interrupts. ste(4) can generate more than 70k RX
interrupts under heavy RX traffics such that these excessive
interrupts make system useless to process other useful things.
Maybe this was the major reason why polling support code was
introduced to ste(4).
The STE_COUNTDOWN register provides a programmable counter that
will generate an interrupt upon its expiration. We program
STE_DMACTL register to use 3.2us clock rate to drive the counter
register. Whenever ste(4) serves RX interrupt, the driver rearm
the timer to expire after STE_IM_RX_TIMER_DEFAULT time and disables
further generation of RX interrupts. This trick seems to work well
and ste(4) generates less than 8k RX interrupts even under 64 bytes
UDP torture test. Combined with TX interrupts, the total number of
interrupts are less than 10k which looks reasonable on heavily
loaded controller.

The default RX interrupt moderation time is 150us. Users can change
the value at any time with dev.ste.%d.int_rx_mod sysctl node.
Setting it 0 effectively disables the RX interrupt moderation
feature. Now we have both TX/RX interrupt moderation code so remove
loop of interrupt handler which resulted in sub-optimal performance
as well as more register accesses.
2009-12-24 17:22:15 +00:00
yongari
f417257f2a We don't need to generate DMA complete interrupt for every
transmitted frames. So request interrupt for every 16th frames. Due
to the limitation of hardware we can't suppress the interrupt as
driver should have to check TX status register. The TX status
register can store up to 31 TX status so driver can't send more
than 31 frames without reading TX status register.
With this change controller would not generate TX completion
interrupt for every frame, so reclaim transmitted frames in
ste_tick().
2009-12-23 19:38:22 +00:00
yongari
415876f659 Correct STE_COUNTDOWN register offset. The datasheet was wrong. 2009-12-23 19:26:38 +00:00
yongari
ec5cce9b74 Remove unused duplicated register definition. It seems the
definition was made to access STE_ASICCTL register as 16bits but
ste(4) always access the register as 32bits so it was never used
before.
2009-12-23 19:21:37 +00:00
yongari
35c91df5a7 Implement hardware MAC statistics counter support. The counters
could be accessed with dev.ste.0.stats sysctl node.
2009-12-23 19:18:07 +00:00
yongari
6b7d7d8935 Reimplement Tx status error handler as recommended by datasheet.
If ste(4) encounter TX underrun or excessive collisions the TX MAC
of controller is stalled so driver should wake it up again. TX
underrun requires increasing TX threshold value to minimize
further TX underruns. Previously ste(4) used to reset controller
to recover from TX underrun, excessive collision and reclaiming
error. However datasheet says only TX underrun requires resetting
entire controller. So implement ste_restart_tx() that restarts TX
MAC and do not perform full reset except TX underrun case.
Now ste(4) uses CSR_READ_2 instead of CSR_READ_1 to read
STE_TX_STATUS register. This way ste(4) will also read frame id
value and we can write the same value back to STE_TX_FRAMEID
register instead of overwriting it to 0. The datasheet was wrong
in write back of STE_TX_STATUS so add some comments why we do so.
Also always invoke ste_txeoc() after ste_txeof() in ste_poll as
without reading TX status register can stall TX MAC.
2009-12-22 23:57:10 +00:00
yongari
4918b61e08 Prefer bus_write_{1,2,4}/bus_read_{1,2,4} to
bus_space_write_{1,2,4}/bus_space_read_{1,2,4}.
Remove unused ste_bhandle and ste_btag in softc.
2009-12-22 21:44:25 +00:00
yongari
f32eb4d51a Prefer memory space register mapping over io space. If memory space
mapping fails fall back to old io space mapping.
While I'm here use PCIR_BAR macro.
2009-12-22 21:39:34 +00:00
yongari
036ec4b1ff Reimplement miibus_statchg method. Don't rely on link state change
interrupt. If we want to use link state change interrupt ste(4)
should also implement auto-negotiation complete handler as well as
various PHY access handling. Now link state change is handled by
mii(4) polling so it will automatically update link state UP/DOWN
events which in turn make ste(4) usable with lagg(4).

r199559 added a private timer to drive watchdog and the timer also
used to drive MAC statistics update. Because the MAC statistics
update is called whenever statistics counter reaches near-full, it
drove watchdog timer too fast such that it caused false watchdog
timeouts under heavy TX traffic conditions.
Fix the regression by separating ste_stats_update() from driving
watchdog timer and introduce a new function ste_tick() that handles
periodic job such as driving watchdog, MAC statistics update and
link state check etc.
While I'm here clear armed watchdog timer in ste_stop().
2009-12-22 20:11:56 +00:00
yongari
804c7f3ed4 Introduce sc_flags member variable and use it to keep track of
link state and PHY related information.
Remove ste_link and ste_one_phy variable of softc as it's not used
anymore.
While I'm here add IFF_DRV_RUNNING check in ste_start_locked().
2009-12-22 19:32:16 +00:00
yongari
a9158a088f Add bus_dma(9) and endianness support to ste(4).
o Sorted includes and added missing header files.
 o Added basic endianness support. In theory ste(4) should work on
   any architectures.
 o Remove the use of contigmalloc(9), contigfree(9) and vtophys(9).
 o Added 8 byte alignment limitation of TX/RX descriptor.
 o Added 1 byte alignment requirement for TX/RX buffers.
 o ste(4) controllers does not support DAC. Limit DMA address space
   to be within 32bit address.
 o Added spare DMA map to gracefully recover from DMA map failure.
 o Removed dead code for checking STE_RXSTAT_DMADONE bit. The bit
   was already checked in each iteration of loop so it can't be true.
 o Added second argument count to ste_rxeof(). It is used to limit
   number of iterations done in RX handler. ATM polling is the only
   consumer.
 o Removed ste_rxeoc() which was added to address RX stuck issue
   (cvs rev 1.66). Unlike TX descriptors, ST201 supports chaining
   descriptors to form a ring for RX descriptors. If RX descriptor
   chaining is not supported it's possible for controller to stop
   receiving incoming frames once controller pass the end of RX
   descriptor which in turn requires driver post new RX
   descriptors to receive more frames. For TX descriptors which
   does not support chaning, we exactly do manual chaining in
   driver by concatenating new descriptors to the end of previous
   TX chain.
   Maybe the workaround was borrowed from other drivers that does
   not support RX descriptor chaining, which is not valid for ST201
   controllers. I still have no idea how this address RX stuck
   issue and I can't reproduce the RX stuck issue on DFE-550TX
   controller.
 o Removed hw.ste_rxsyncs sysctl as the workaround was removed.
 o TX/RX side bus_dmamap_load_mbuf_sg(9) support.
 o Reimplemented optimized ste_encap().
 o Simplified TX logic of ste_start_locked().
 o Added comments for TFD/RFD requirements.
 o Increased number of RX descriptors to 128 from 64. 128 gave much
   better performance than 64 under high network loads.
2009-12-22 18:57:07 +00:00
yongari
ea15f0871d Remove trailing white spaces. 2009-12-21 20:02:12 +00:00
yongari
bfa95b94ce s/u_intXX_t/uintXX_t/g 2009-12-21 20:00:27 +00:00
jhb
affabaa85e - Add a private timer to drive the transmit watchdog instead of using
if_watchdog and if_timer.
- Fix some issues in detach for sn(4), ste(4), and ti(4).  Primarily this
  means calling ether_ifdetach() before anything else.
2009-11-19 22:06:40 +00:00
imp
5c156fea13 Move the ste driver from sys/pci to sys/dev/ste. 2008-08-14 20:09:58 +00:00