Commit Graph

464 Commits

Author SHA1 Message Date
raj
b729364e00 Rework BookE pmap towards multi-core support.
o Eliminate tlb0[] (a s/w copy of TLB0)
  - The table contents cannot be maintained reliably in multiple MMU
    environments, where asynchronous events (invalidations from other cores)
    can change our local TLB0 contents underneath.
  - Simplify and optimize TLB flushing: system wide invalidations are
    performed using tlbivax instruction (propagates to other cores), for
    local MMU invalidations a new optimized routine (assembly) is introduced.

o Improve and simplify TID allocation and management.
  - Let each core keep track of its TID allocations.
  - Simplify TID recycling, eliminate dead code.
  - Drop the now unused powerpc/booke/support.S file.

o Improve page tables management logic.

o Simplify TLB1 manipulation routines.

o Other improvements and polishing.

Obtained from:	Freescale, Semihalf
2009-01-13 15:41:58 +00:00
nwhitehorn
3fcef6d9c2 Modularize the Open Firmware client interface to allow run-time switching
of OFW access semantics, in order to allow future support for real-mode
OF access and flattened device frees. OF client interface modules are
implemented using KOBJ, in a similar way to the PPC PMAP modules.

Because we need Open Firmware to be available before mutexes can be used on
sparc64, changes are also included to allow KOBJ to be used very early in
the boot process by only using the mutex once we know it has been initialized.

Reviewed by:    marius, grehan
2008-12-20 00:33:10 +00:00
raj
d71801145e Improve MPC85XX helper routines.
- Move CCSR accessors to the shared MPC85XX area
- Simplify SVR version subfield handling
- Adjust OCP
2008-12-17 15:27:49 +00:00
imp
39a3668dcc AT_DEBUG and AT_BRK were OBE like 10 years ago, so retire them.
Reviewed by:	peter
2008-12-17 06:56:58 +00:00
nwhitehorn
f0e837432d Adapt parts of the sparc64 Open Firmware bus enumeration code (in particular,
the code for parsing interrupt maps) to PowerPC and reflect their new MI
status by moving them to the shared dev/ofw directory.

This commit also modifies the OFW PCI enumeration procedure on PowerPC to
allow the bus to find non-firmware-enumerated devices that Apple likes to add,
and adds some useful Open Firmware properties (compat and name) to the pnpinfo
string of children on OFW SBus, EBus, PCI, and MacIO links. Because of the
change to PCI enumeration on PowerPC, X has started working again on PPC
machines with Grackle hostbridges.

Reviewed by:	marius
Obtained from:	sparc64
2008-12-15 15:31:10 +00:00
marcel
080c5cc425 Unbreak previous commit. 2008-11-22 22:15:34 +00:00
kmacy
9d3bb599b1 - bump __FreeBSD version to reflect added buf_ring, memory barriers,
and ifnet functions

- add memory barriers to <machine/atomic.h>
- update drivers to only conditionally define their own

- add lockless producer / consumer ring buffer
- remove ring buffer implementation from cxgb and update its callers

- add if_transmit(struct ifnet *ifp, struct mbuf *m) to ifnet to
  allow drivers to efficiently manage multiple hardware queues
  (i.e. not serialize all packets through one ifq)
- expose if_qflush to allow drivers to flush any driver managed queues

This work was supported by Bitgravity Inc. and Chelsio Inc.
2008-11-22 05:55:56 +00:00
marcel
39fb5ed1d3 Define LDBL_EPSILON, LDBL_MAX and LDBL_MIN as long double constants.
Submitted by:	Andreas Tobler <andreast-list@fgznet.ch>
Reviewed by:	das@
2008-11-16 19:20:29 +00:00
sobomax
ae5a12cdf1 Fix compilation in the case when kernel doesn't have KDB ebabled.
subr_kdb.c still references breakpoint() in this case.
2008-10-30 21:02:00 +00:00
marcel
64f5c79806 Add support for little-endian compilations to this file. 2008-10-30 03:31:33 +00:00
marcel
322737440f Add support for kernel profiling for both AIM and BookE.
Obtained from:	Juniper Networks, Inc (BookE support).
2008-10-27 02:36:03 +00:00
marcel
460ad2e4b2 Declare btext and etext. Needed by sys/kern/subr_prof.c for
for kernel profiling.
2008-10-27 00:26:07 +00:00
nwhitehorn
0d091e41de Convert PowerPC AIM PCI and nexus busses to standard OFW bus interface. This
simplifies certain device attachments (Kauai ATA, for instance), and makes
possible others on new hardware.

On G5 systems, there are several otherwise standard PCI devices
(Serverworks SATA) that will not allow their interrupt properties to be
written, so this information must be supplied directly from Open Firmware.

Obtained from:	sparc64
2008-10-14 14:54:14 +00:00
marius
a1ec700ce8 Remove ipi_all() and ipi_self() as the former hasn't been used at
all to date and the latter also is only used in ia64 and powerpc
code which no longer serves a real purpose after bring-up and just
can be removed as well. Note that architectures like sun4u also
provide no means of implementing IPI'ing a CPU itself natively
in the first place.

Suggested by:	jhb
Reviewed by:	arch, grehan, jhb
2008-09-28 18:34:14 +00:00
nwhitehorn
e873cabccd Expand the DBDMA API to allow setting device-dependent control bits. While
here, clean up and document this a little.

Submitted by:	Marco Trillo
MFC after:	1 week
2008-09-27 15:41:16 +00:00
nwhitehorn
2a5e536b9e Allow the cacheline size on PowerPC to be set at runtime. This is essential for
supporting 64-bit CPUs, which often have 128-byte cache lines instead of the
standard 32.
2008-09-24 00:28:46 +00:00
nwhitehorn
d5de411ace In preparation for PowerPC G5 support, allow PVO objects to contain page
table entries for both the 32-bit and 64-bit AIM MMUs.
2008-09-23 03:02:57 +00:00
nwhitehorn
4c77244de0 Change the DBDMA API to allow DBDMA registers in a subregion of a resource. This is necessary to allow future support of DMA for the various Apple on-board ATA controllers.
MFC after:	1 week
2008-09-23 02:12:47 +00:00
marcel
30ff2246e9 In powerpc_get_pcpup(), make the inline assembly statement
volatile so that the compiler won't perform CSE. For SMP,
this may result in us accessing the wrong PCPU and as such
results in a bogus curthread value.

Note that getting curthread is not quite MP-safe in the sense
that it requires two instructions that aren't performed
atomically. The first instruction gets the address of the PCPU
structure and the second instruction dereferences that pointer
to get curthread. If a thread is switched-out in between these
instructions and switched-in on a different CPU, we still get
the wrong curthread.
2008-09-16 16:28:51 +00:00
marcel
1e7ba9e4d7 Remove the tracing from the AP startup. The AP is known
to start and the tracing can interfere with AP startup.
Instead, use the available space in the reset vector
for the initial stack.
2008-09-16 01:05:54 +00:00
marcel
1beb54fb0c o Remove SPR_TSR & SPR_TCR for AIM.
o  Remove SPR_HID2.
o  Add more SPR_L3CR bit definitions.
2008-09-15 02:51:07 +00:00
marcel
6745d3f73c Remove restore_intr(). We have intr_restore()... 2008-08-31 02:25:20 +00:00
marcel
7cf0ef569d Add powerpc_sync() as an inline function. 2008-08-30 18:38:37 +00:00
jhb
d90774443d Export 'struct pcpu' to userland w/o requiring _KERNEL. A few ports
already define _KERNEL to get to this and I'm about to add hooks to
libkvm to access per-CPU data.

MFC after:	1 week
2008-08-19 19:53:52 +00:00
ed
60aa8a602b Remove the unused M_MEMDEV from the kernel.
The M_MEMDEV memory allocation pool does not seem to be used. We can
live without it.

Approved by:	philip (mentor)
2008-06-25 07:52:10 +00:00
ed
4d6a9685e8 Remove the unused major/minor numbers from iodev and memdev.
Now that st_rdev is being automatically generated by the kernel, there
is no need to define static major/minor numbers for the iodev and
memdev. We still need the minor numbers for the memdev, however, to
distinguish between /dev/mem and /dev/kmem.

Approved by:	philip (mentor)
2008-06-25 07:45:31 +00:00
marcel
7cc97ffd51 Add support for Apple's Descriptor-Based DMA (DBDMA) engine. The DMA
engine is usful to various  existing drivers, such as ata(4) and scc(4),
and is used bhy the soon to be added bm(4).

Submitted by:	Nathan Whitehorn
2008-06-07 21:56:48 +00:00
marcel
20ca53a7f4 MFp4: SMP support 2008-04-27 22:33:43 +00:00
marcel
61b6f3e4f9 MFp4: SMP support 2008-04-27 19:51:34 +00:00
marcel
33096044a3 Remove mfsvr():
o  The function is defined unconditionally but depends on SPR_SVR,
   which is defined conditionally.
o  spr.h defines mfspr() and mtspr(), which is no worse to use.
2008-04-27 17:13:22 +00:00
raj
a681868ea5 Improve handling of Local Access Windows on MPC85xx systems:
- detect number of LAWs in run time and initalize accordingly
- introduce decode windows target IDs used in MPC8572
- other minor updates

Obtained from:	Freescale, Semihalf
2008-04-26 17:47:28 +00:00
raj
08c272026d Move System Revision defines to a bit better place, add MPC8572 systems IDs. 2008-04-26 17:39:55 +00:00
marcel
5c68af8d1f Fix copy-n-paste typos in free text. 2008-04-10 02:37:26 +00:00
marcel
70b66c6276 Reimplement atomic_add, atomic_clear, atomic_set and atomic_subtract
so that all implemented variants have proper prototypes. The 8-bit,
16-bit and 64-bit variants are not implemented.

This really fixes the current build breakages caused by type casting
and struct aliasing rules.
2008-04-09 01:00:35 +00:00
marcel
db3fbb6a27 Quick fix for the kernel build breakage in netgraph and the
aliasing warning in libthr. A more elaborate fix is in the
works that makes sure that all variants have proper inline
functions with proper types.
2008-04-08 16:34:50 +00:00
marcel
7dc245de4b Align functions to 16-byte boundaries due to profiling granularity. 2008-04-03 17:40:20 +00:00
jb
34e730ca27 When building a kernel module, define MAXCPU the same as SMP so
that modules work with and without SMP.
2008-03-27 05:03:26 +00:00
phk
fa71439e44 The "free-lance" timer in the i8254 is only used for the speaker
these days, so de-generalize the acquire_timer/release_timer api
to just deal with speakers.

The new (optional) MD functions are:
	timer_spkr_acquire()
	timer_spkr_release()
and
	timer_spkr_setfreq()

the last of which configures the timer to generate a tone of a given
frequency, in Hz instead of 1/1193182th of seconds.

Drop entirely timer2 on pc98, it is not used anywhere at all.

Move sysbeep() to kern/tty_cons.c and use the timer_spkr*() if
they exist, and do nothing otherwise.

Remove prototypes and empty acquire-/release-timer() and sysbeep()
functions from the non-beeping archs.

This eliminate the need for the speaker driver to know about
i8254frequency at all.  In theory this makes the speaker driver MI,
contingent on the timer_spkr_*() functions existing but the driver
does not know this yet and still attaches to the ISA bus.

Syscons is more tricky, in one function, sc_tone(), it knows the hz
and things are just fine.

In the other function, sc_bell() it seems to get the period from
the KDMKTONE ioctl in terms if 1/1193182th second, so we hardcode
the 1193182 and leave it at that.  It's probably not important.

Change a few other sysbeep() uses which obviously knew that the
argument was in terms of i8254 frequency, and leave alone those
that look like people thought sysbeep() took frequency in hertz.

This eliminates the knowledge of i8254_freq from all but the actual
clock.c code and the prof_machdep.c on amd64 and i386, where I think
it would be smart to ask for help from the timecounters anyway [TBD].
2008-03-26 20:09:21 +00:00
marcel
380d312794 Make remote GDB work for AIM processors. For BookE, the kernel
will have a special section, named .PPC.EMB.apuinfo, which will
tell GDB that a BookE processor is targeted and which will
result in GDB using a different register definition. In order
to support remote GDB for BookE, we need the GDB stub in the
kernel look for that section and use the BookE definitions.
2008-03-17 00:46:52 +00:00
pjd
ea49d310bf Implement atomic_fetchadd_long() for all architectures and document it.
Reviewed by:	attilio, jhb, jeff, kris (as a part of the uidinfo_waitfree.patch)
2008-03-16 21:20:50 +00:00
raj
8e81cff1fe Obtain TSEC h/w address from the parent bus (OCP) and not rely blindly on what
might be currently programmed into the registers.

Underlying firmware (U-Boot) would typically program MAC address into the
first unit only, and others are left uninitialized. It is now possible to
retrieve and program MAC address for all units properly, provided they were
passed on in the bootinfo metadata.

Reviewed by:	imp, marcel
Approved by:	cognet (mentor)
2008-03-12 16:32:08 +00:00
marcel
37503bed38 For AIM, have cpu_idle() set MSR_POW when the powerpc_pow_enabled
variable is set. On my Mac Mini this puts the CPU in NAP mode when
the kernel is idle and, any technical or environmental reasons
aside, avoids that I have to listen to the fan all day :-)
2008-03-07 22:27:06 +00:00
marcel
df20e17353 Add support for the BUS_CONFIG_INTR() method to the platform and to
openpic(4). Make use of it in ocpbus(4). On the MPC85xxCDS, IRQ0:4
are active-low.
2008-03-07 22:08:43 +00:00
marcel
d0e9f0f0d1 Add a catch-all for PCPU_MD_FIELDS. While we expect this to be
used in the kernel only (by virtue of checking for _KERNEL),
ports like lsof (part of gtop) cheat. It sets _KERNEL, but does
not set either AIM or E500. As such, PCPU_MD_FIELDS didn't get
defined and the build broke.
The catch-all is to define PCPU_MD_FIELDS with a dummy integer
when at the end of line we ended up without a definition for it.
2008-03-06 16:59:36 +00:00
raj
0757a4afb5 Initial support for Freescale PowerQUICC III MPC85xx system-on-chip family.
The PQ3 is a high performance integrated communications processing system
based on the e500 core, which is an embedded RISC processor that implements
the 32-bit Book E definition of the PowerPC architecture. For details refer
to: http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC8555E

This port was tested and successfully run on the following members of the PQ3
family: MPC8533, MPC8541, MPC8548, MPC8555.

The following major integrated peripherals are supported:

  * On-chip peripherals bus
  * OpenPIC interrupt controller
  * UART
  * Ethernet (TSEC)
  * Host/PCI bridge
  * QUICC engine (SCC functionality)

This commit brings the main functionality and will be followed by individual
drivers that are logically separate from this base.

Approved by:	cognet (mentor)
Obtained from:	Juniper, Semihalf
MFp4:		e500
2008-03-03 17:17:00 +00:00
raj
05437e53d5 Rework and extend PowerPC headers definitons towards Book-E/e500 CPUs support.
Approved by:	cognet (mentor)
Obtained from:	Juniper, Semihalf
MFp4:		e500
2008-03-03 13:20:52 +00:00
raj
3dea77f93c Unify and generalize PowerPC headers, adjust AIM code accordingly.
Rework of this area is a pre-requirement for importing e500 support (and
other PowerPC core variations in the future). Mainly the following
headers are refactored so that we can cover for low-level differences between
various machines within PowerPC architecture:

  <machine/pcpu.h>
  <machine/pcb.h>
  <machine/kdb.h>
  <machine/hid.h>
  <machine/frame.h>

Areas which use the above are adjusted and cleaned up.

Credits for this rework go to marcel@

Approved by:	cognet (mentor)
MFp4:		e500
2008-03-02 17:05:57 +00:00
raj
ec4d22c527 Teach PowerPC CPU identification routines to recognize e500 cores. Fix style
issues in this area.

Approved by:	cognet (mentor)
MFp4:		e500
2008-02-25 00:09:23 +00:00
raj
69575dab52 Let PowerPC world optionally build with -msoft-float. For FPU-less PowerPC
variations (e500 currently), this provides a gcc-level FPU emulation and is an
alternative approach to the recently introduced kernel-level emulation
(FPU_EMU).

Approved by:	cognet (mentor)
MFp4:		e500
2008-02-24 19:22:53 +00:00
marcel
2c03940da7 Define the bootinfo structure for FreeBSD. It is not used on
AIM, but it's used for BookE.
2008-02-23 18:01:45 +00:00