In n32 and n64, add support for physical address above 4GB by having
64 bit page table entries and physical addresses. Major changes are:
- param.h: update PTE sizes, masks and shift values to support 64 bit PTEs.
- param.h: remove DELAY(), mips_btop(same as atop), mips_ptob (same as
ptoa), and reformat.
- param.h: remove casting to unsigned long in trunc_page and round_page
since this will be used on physical addresses.
- _types.h: have 64 bit __vm_paddr_t for n32.
- pte.h: update TLB LO0/1 access macros to support 64 bit PTE
- pte.h: assembly macros for PTE operations.
- proc.h: md_upte is now 64 bit for n32 and n64.
- exception.S and swtch.S: use the new PTE macros for PTE operations.
- cpufunc.h: TLB_LO0/1 registers are 64bit for n32 and n64.
- xlr_machdep.c: Add memory segments above 4GB to phys_avail[] as they are
supported now.
Reviewed by: jmallett (earlier version)
the ones which run the message ring handler.
Some bits of the interrupt mask are part of the status register which is
saved with the process context, and these bits are initialized from the
cpu on which the process is created. This means that all the processes
should have the same value for these interrupt mask bits, so that the
interrupt mask remains the same regardless of what thread is scheduled
on the cpu.
Submitted by: Sriram Gorti (srgorti at netlogicmicro dot com)
- ds1374u : use multi-byte write.
- at24co2n, max6657: remove mutex, iicbus has the necessary locking.
Submitted by: Sreekanth M. S. (kanthms at netlogicmicro com)
1) 32-bit assignment are expected to always be atomic.
2) Release/acquire memory barrier semantics doesn't seem to be needed here.
So a simple assignment can be used.
Remove unused port_set_counter() while here, it also used to mis-use
atomic_set_int().
Reported by: jhb
Pointyhat to: avg
MFC after: 3 weeks
- Major update to xlr_i2c.c: do multi-byte ops correctly, remove unnecessary
code, add mutex to protect bus operations, style(9) fixes.
- Drivers for I2C devices on XLR/XLS engineering boards, ds1374u RTC, max6657
temparature sensor and at24co2n EEPROM.
Submitted by: Sreekanth M. S. (kanthms at netlogicmicro com)
- remove unused code in mips/rmi/xlr_pci.c
- remove unused variable in mips/rmi/dev/nlge/if_nlge.c
- fix reference to old function in mips/mips/pmap.c
Reported by: Prabhath Raman (prabhath at netlogicmicro com)
DPCPU_DEFINE and VNET_DEFINE macros, as these cause problems for various
people working on the affected files. A better long-term solution is
still being considered. This reversal may give some modules empty
set_pcpu or set_vnet sections, but these are harmless.
Changes reverted:
------------------------------------------------------------------------
r215318 | dim | 2010-11-14 21:40:55 +0100 (Sun, 14 Nov 2010) | 4 lines
Instead of unconditionally emitting .globl's for the __start_set_xxx and
__stop_set_xxx symbols, only emit them when the set_vnet or set_pcpu
sections are actually defined.
------------------------------------------------------------------------
r215317 | dim | 2010-11-14 21:38:11 +0100 (Sun, 14 Nov 2010) | 3 lines
Apply the STATIC_VNET_DEFINE and STATIC_DPCPU_DEFINE macros throughout
the tree.
------------------------------------------------------------------------
r215316 | dim | 2010-11-14 21:23:02 +0100 (Sun, 14 Nov 2010) | 2 lines
Add macros to define static instances of VNET_DEFINE and DPCPU_DEFINE.
the NIC drivers as well as the PHY drivers to take advantage of the
mii_attach() introduced in r213878 to get rid of certain hacks. For
the most part these were:
- Artificially limiting miibus_{read,write}reg methods to certain PHY
addresses; we now let mii_attach() only probe the PHY at the desired
address(es) instead.
- PHY drivers setting MIIF_* flags based on the NIC driver they hang
off from, partly even based on grabbing and using the softc of the
parent; we now pass these flags down from the NIC to the PHY drivers
via mii_attach(). This got us rid of all such hacks except those of
brgphy() in combination with bce(4) and bge(4), which is way beyond
what can be expressed with simple flags.
While at it, I took the opportunity to change the NIC drivers to pass
up the error returned by mii_attach() (previously by mii_phy_probe())
and unify the error message used in this case where and as appropriate
as mii_attach() actually can fail for a number of reasons, not just
because of no PHY(s) being present at the expected address(es).
Reviewed by: jhb, yongari
physical address. Adds a dma tag to the XLR/XLS pci bus with the
lowaddr if the CPU happens to be a XLR C rev.
Submitted by: Sreekanth M. S. (kanthms at netlogicmicro dot com))
- nlge_ioctl handles IFF_UP and IFF_PROMISC flags
- Translate table code, to enable flow based CPU assignment added
disabled by default (can be enabled by a tunable).
- Changed signature of nlge_port_disable to make it consistent with nlge_port_enable
- Removed TXCSUM and VLAN_HW_TAGGING from i/f capabilities.
Submitted by: Sriram Gorti (srgorti at netlogicmicro dot com)
sysctl and counters for message ring threads (intial version). Update
watermark values, and and decrease the maximum threads to 3 (this will leave
a few CPUs for other processes)
Minor comment fix in nlge.
- Wakeup multiple threads per core using message ring watermark interrupts.
- Update message ring handler registration, use the real device station id
for registering interrupts.
- rge/nlge: update for the new message ring registration code.
- rge/nlge: use 2 message ring stations for incoming packets, this will
allow more messages to be queued.
- nlge: comment fixes, remove unused variable
- style and whitespace fixes
- XLS B0 and later revision chips have PCIe link 2 & 3 mapped to different
PIC interrupts. Update pic.h, board.h and xlr_pci.c to reflect this.
- remove debug prints in xlr_pci.c
- add more processor IDs to board.h, add function xlr_is_xls_b0()
- some style(9) and whitespace fixes
- 64 bit fixes for ifnlge.c
- Use m_nextpkt to save mbuf vaddr on 64 bit, we cannot store the
64 bit vaddr in the 40bit freeback field.
- remove unused code and unnecessary variables.
- use xlr_io_mmio macro instead of adding io base address
- rewrite GPIO related code to fixup nlge using xlr_write_reg and DELAY
- support for engg boards major num 11 and 12
- add xlr_paddr_lw() to load 32bit value from physical address, fix
inline assembly
- style fixes
- Process some tx done messages in the transmit path, to ensure that
the XLR NA tx done FIFO does not overflow.
- Add a message ring handler API to process atmost a given number of
messages from a specified bucket mask. This will be used to process
the tx done messages
- Add a callout to restart transmit in the case transmit gets blocked.
- Update enable_msgring_int() and disable_msgring_int(), remove unused
args and make static.
Obtained from: Sriram Gorti (srgorti at netlogicmicro dot com)
- Compile fixes for 9.0, the previous version of this driver was
for FreeBSD 6.
- Add virtual address field in OperationDescriptor_t, we cannot use
MIPS_PHYS_TO_KSEG0 on physical address.
- Fixes for new message ring API
- Remove unused sys/mips/rmi/dev/sec/stats.h
- Whitespace fixes
- Move RMI MIPS extension to atomic increment word (LDADDWU) to common
header file sys/mips/rmi/rmi_mips_exts.h
- Fix xlr_ldaddwu() for 64 bit, it is a 32 bit operation, use
unsigned int* instead of unsigned long* argument
- Provide dummy xlr_enable_kx/xlr_restore_kx for n32 and n64.
- Provide xlr_paddr_ld() instead of xlr_paddr_lw(), so that the
descriptor formats are same for 32 and 64 bit
- update nlge and rge for the changes
These changes are also needed by the security driver which will be
added later.
- Remove sync from msgrng_send, sync needs to be called just once before
sending.
- Fix retry logic - don't reload registers when retrying in message_send,
also fix check for send pending fail.
- remove unused message_send_block_fast()
- merge message_receive_fast() to message_receive
- style(9) fixes, and comments
- rge and nlge updated for the sys/mips/rmi/msgring.h changes
- Provide 64 bit implementations for some macros. On n64 and n32,
don't split 64 bit values.
- No need for 32 bit ops for control registers.
- Fix few bugs (write control reg, write_c0_register64).
- Re-write EIRR/EIMR/CPUID operations using read_c0_registerXX, no
need of inline assembly.
- rename control reg access functions to avoid phnx, update callers.
- stlye/whitespace fixes.
- Updates for the message ring clean up in r212321.
- Instead of dropping Tx packet on credit fail, retry send until it
succeeds.
- Fix freeing mbufs in case of P2P descriptors:
We cannot free the mbuf when the P2P descriptor freeback is received. The
mbuf may be still in use by the GMAC, since the P2P freeback indicates that
it read the P2D descriptors in the P2P message.
Now we free just the P2P descriptor when the P2P freeback message is
received. Another freeback P2D message has been added to the end of
the packet descriptors, the mbuf will be freed only when we received
this.
The P2P descriptor issue was reported by srgorti at netlogicmicro dot com.
Fix message ring send path:
- define msgrng_access_enable() which disables local interrupts
and enables message ring access. Also define msgrng_restore() which
restores interrupts
- remove all other msgrng enable/disable macros, no need of critical_enter
and other locking here.
- message_send() fixup: re-read status until pending bit clears
- message_send_retry() fixup: retry only few times with interrupts disabled
- Fix up message_send/message_send_retry callers - call
msgrng_access_enable() and msgrng_restore() correctly so that interrupts
are not disabled for long.
- removed unused and obsolete code from sys/mips/rmi/msgring.h
- some style fixes - more later
rge.c (XLR GMAC driver):
- updated for the message ring changes
- remove unused message_send_block()
- retry on credit failure, this is not a permanent failure when credits
are configured correctly. Add panic if credits are not available to
send for a long time.
Fix interrupt routing so that the irq returned is correct for XLR and
XLS. This also updates the MSI hack we had earlier - we still don't
really support MSI, but we support some drivers that use MSI, by providing
support for allocating one MSI per pci link - this MSI is directly
mapped to the link IRQ.
- set cache_coherent_dma flag in cpuinfo for XLR, this will make sure that
BUS_DMA_COHERENT flag is handled correctly in busdma_machdep.c
- iodi.c, call device_get_name() just once
- clear RMI specific EIRR while intializing CPUs
- remove debug print in intr_machdep.c
unused files.
- remove clock.c and clock.h, these are not used after the new timer
code was added.
- remove duplicated include files, fix header file ordering, remove
some unneeded includes.
- rename mips/rmi/shared_structs.h which contains the RMI boot loader
interface to mips/rmi/rmi_boot_info.h. Remove unused files
mips/rmi/shared_structs_func.h and sys/mips/rmi/shared_structs_offsets.h
- merge mips/rmi/xlrconfig.h and mips/rmi/rmi_mips_exts.h, and remove
duplicated functions.
- nlge - minor change to remove unneeded argument.
- Add FreeBSD svn keyword for headers
and XAUI 10G interfaces in addition RGMII/SGMII 1G interfaces. This driver
is work in progress.
board.c and board.h expanded to include more info.
Only one of rge and nlge can be enabled at a time, rge will be deprecated
when nlge stabilizes.
Submitted by: Sriram Gorti <srgorti at netlogicmicro com>
SMP.
We used to route all PIC based interrupts to cpu 0, and used the per-CPU
interrupt mask to enable/disable interrupts. But the interrupt threads can
run on any cpu on SMP, and the interrupt thread will re-enable the interrupts
on the CPU it runs on when it is done, and not on cpu0 where the PIC will
still send interrupts to.
The fix is move the disable/enable for PIC based interrupts to PIC, we will
ack on PIC only when the interrupt thread is done, and we do not use the
per-CPU interrupt mask.
The changes also introduce a way for subsystems to add a function that
will be called to clear the interrupt on the subsystem. Currently This is
used by the PCI/PCIe for doing additional work during the interrupt
handling.
- Use timer 7 in XLR PIC as a 32 counter
- provide pic_init_timer(), pic_set_timer(), pic_timer_count32() and
pic_timer_count() PIC timer operations.
- register this timer as platform_timecounter on rmi platform.
- style(9) fixes to mips/rmi platform files
- update pic.h to add pic_setup_intr() and use pic_setup_intr() for setting
up interrupts which are routed thru PIC.
- remove rmi_spin_mutex_safe and haslock, and make sure that the functions
are called only after mutexes are available.
- move PIC code to xlr_machdep.c
- move fast message ring code completely to on_chip.c
- move memory initialization to a new function xlr_mem_init()
- style fixes
booting again.
The code is a copy of the mips/mips/tick.c with minor modifications for
XLR interrupt handling. Disable mips/rmi/clock.c for now, the PIC based
timer code will be added later.
- Adds re-partitioning TLB per core for enabled threads.
- Adds hardware thread id to cpuid mapping
- updates rge driver packet distribution and message ring handling
threads to be started based on hardware thread id.
- remove unused early debugging code to set control registers.
- coding style fixes
Approved by: rrs (mentor)
am now able to run 32 cores ok.. but I still will hang
on buildworld with a NFS problem. I suspect I am missing
a patch for the netlogic rge driver.
JC check and see if I am missing anything except your
core-mask changes
Obtained from: JC
ones implemented using assembly.
o) Use TRAPF_USERMODE() consistently rather than USERMODE(). Eliminate
<machine/psl.h> as a result.
o) Use intr_*() rather than *intr(), consistently.
o) Use register_t instead of u_int in some trap code.
o) Merge some more endian-related macros to machine/asm.h from NetBSD.
o) Add PTR_LI macro, which loads an address with the correct sign-extension for
a pointer.
o) Restore interrupts when bailing out due to an excessive IRQ in
nexus_setup_intr().
o) Remove unused functions from psraccess.S.
o) Enter temporary virtual entries for large memory access into the page tables
rather than simply hoping they stay resident in the TLB and we don't need to
do a refill for them.
o) Abstract out large memory mapping setup/teardown using some macros.
o) Do mips_dcache_wbinv_range() when using temporary virtual addresses just
like we do when we can use the direct map.
- remove unused and commented code (MIPS_BUS_SPACE_PCI, pic_usb_ack)
- use rmi_pci_bus_space for USB too (needs byteswap)
- uncomment xls_ehci.c in files.xlr
- changes to xls_ehci.c - updated with dev/usb/controller/ehci_*.c as
Obtained from: JC - c.jayachandran@gmail.com
- add bus_space_rmi_pci.c for PCI bus space
- files.xlr update for changes in files
- pcibus.c merged into xlr_pci.c (they were small files with inter-dependencies)
- xlr_pci.c - lot of changes here with few fixes, formatting cleanup
Obtained from: C. Jayachandran (JC) - c.jayachandran@gmail.com
- remove pci related code from bus_space_rmi.c, we will have another
file for PCI bus space functions which will do byte-swapping.
- remove local SWAP implementation
- added TODO stub for unimplemented functions
Obtained from: C. Jayachandran - c.jayachandran@gmail.com
- (cleanup) remove rmi specific 'struct mips_intrhand' - this is no
longer needed since 'struct intr_event' have all the required hooks
- add xlr_cpu_establish_hardintr, which has args for pre/post ithread
and filter hooks, so that the PCI code can add the PCI controller
interrupt ack code here
- make 'cpu_establish_hardintr' use the above function.
- (fix) change type of eirr/eimr from register_t to uint64_t. These
have to be 64bit otherwise we cannot handle interrupts from 32.
- (fix) use eimr to mask eirr before checking interrupts, so that we
will not handle masked interrupts.
Obtained from: C. Jayachandran - c.jayachandran@gmail.com
have code that detects this and makes two
transmit descriptors. However its possible
that the algorithm detects when the second
page is not used (when the data aligns perfectly
to the bottom of the page). This caused a 0
len descriptor to be added which locks up the
rge device. Skip such things with a continue.
JC provided this patch... Thanks JC :-)
Obtained from: JC (c.jayachandran@gmail.com)
above 4Gig. If so when we add the base address with
the size we will wrap. So for now we just ignore
such memory and only use what we can. When we
get 64 bit working then we will be much better ;->
Basically the msg ring interrupt was being re-enabled
inside a spinlock as the thread set it self up for rescheduling.
This won't work since inside the re-enable is another
spin lock.. which means on return from the reenable
the interrupts have been reenabled. Thus you would
get a clock int and end up panicing holding a spin
lock to long :-o
