Commit Graph

7 Commits

Author SHA1 Message Date
marius
a030d21a6f - USIII-based machines can consist of CPUs running at different
frequencies (and having different cache sizes) so use the STICK
  (System TICK) timer, which was introduced due to this and is
  driven by the same frequency across all CPUs, instead of the
  TICK timer, whose frequency varies with the CPU clock, to drive
  hardclock. We try to use the STICK counter with all CPUs that are
  USIII or beyond, even when not necessary due to identical CPUs,
  as we can can also avoid the workaround for the BlackBird erratum
  #1 there. Unfortunately, using the STICK counter currently causes
  a hang with USIIIi MP machines for reasons unknown, so we still
  use the TICK timer there (which is okay as they can only consist
  of identical CPUs).
- Given that we only (try to) synchronize the (S)TICK timers of APs
  with the BSP during startup, we could end up spinning forever in
  DELAY(9) if that function is migrated to another CPU while we're
  spinning due to clock drift afterwards, so pin to the CPU in order
  to avoid migration. Unfortunately, pinning doesn't work at the
  point DELAY(9) is required by the low-level console drivers, yet,
  so switch to a function pointer, which is updated accordingly, for
  implementing DELAY(9). For USIII and beyond, this would also allow
  to easily use the STICK counter instead of the TICK one here,
  there's no benefit in doing so however.
  While at it, use cpu_spinwait(9) for spinning in the delay-
  functions. This currently is a NOP though.
- Don't set the TICK timer of the BSP to 0 during at startup as
  there's no need to do so.
- Implement cpu_est_clockrate().
- Unfortunately, USIIIi-based machines don't provide a timecounter
  device besides the STICK and TICK counters (well, in theory the
  Tomatillo bridges have a performance counter that can be (ab)used
  as timecounter by configuring it to count bus cycles, though unlike
  the performance counter of Schizo bridges, the Tomatillo one is
  broken and counts Sun knows what in this mode). This means that
  we've to use a (S)TICK counter for timecounting, which has the old
  problem of not being in sync across CPUs, so provide an additional
  timecounter function which binds itself to the BSP but has an
  adequate low priority.
2008-09-03 17:39:19 +00:00
marius
743faad470 - Also identify USIIIi+, USIV and USIV+ CPUs.
- Use __FBSDID in identcpu.c.
- Remove #ifndef SUN4V around global cpu_impl variable; it doesn't
  hurt on sun4v for now and once setPQL2() is gone sun4v can stop
  sharing identcpu.c with sparc64, making the reminder of this file
  also sparc64-only again. [1]

Submitted by:	kmacy [1]
2007-05-20 13:47:36 +00:00
scottl
4beab3afdd Identify USIIIi processors.
Submitted by: Gavin Atkinson
PR: 75468
2004-12-24 16:21:46 +00:00
tmm
e5e9ae1dc2 Add two new workaround for firmware anomalies:
1. At least some Netra t1 models have PCI buses with no associated
   interrupt map, but obviously expect the PCI swizzle to be done with
   the interrupt number from the higher level as intpin. In this case,
   the mapping also needs to continue at parent bus nodes.
   To handle that, add a quirk table based on the "name" property of
   the root node to avoid breaking other boxen. This property is now
   retrieved and printed at boot.
2. On SPARCengine Ultra AX machines, interrupt numbers are not mapped
   at all, and full interrupt numbers (not just INOs) are given in
   the interrupt properties. This is more or less cosmetical; the
   PCI interrupt numbers would be wrong, but the psycho resource
   allocation method would pass the right numbers on anyway.

Tested by:	mux (1), Maxim Mazurok <maxim@km.ua> (2)
2002-11-07 16:07:46 +00:00
jake
5d43846206 Identify UltraSPARC-III and UltraSPARC-III+ cpus. 2002-07-13 03:23:29 +00:00
tmm
1f20dab185 Define constants for the CPU implementation id; export the dectected id
as cpu_impl.
2002-02-13 15:47:12 +00:00
jake
fa2bcfc98d Move %ver definitions from pstate.h to ver.h. Add definitions for normal
kernel pstate values, which include a memory store order override.
2001-09-03 22:36:11 +00:00